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1. 发明授权

US08309957B2 Replacement of scribeline padframe with saw-friendly design 有权
标题翻译：用锯切友好的设计更换模板衬垫
公开(公告)号：US08309957B2
公开(公告)日：2012-11-13
申请号：US12759005
申请日：2010-04-13
申请人： Basab Chatterjee , Jeffrey Alan West , Gregory Boyd Shinn
发明人： Basab Chatterjee , Jeffrey Alan West , Gregory Boyd Shinn
IPC分类号： H01L23/50
CPC分类号： H01L22/34 , G01R31/2884 , H01L2224/05093
摘要： An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.
摘要翻译：一种集成电路基板，其包含在切割切割车道上方并且在其两侧的电探针焊盘结构。电探针焊盘结构包括与切割切口通道相邻的金属裂纹阻止条。断裂条之间的金属密度小于70％。包含金属裂纹阻挡带的电探针垫结构，裂纹阻挡带之间的金属密度小于70％。通过在与集成电路相邻的切割切口通道上形成电探针焊盘结构来形成集成电路的工艺，使得电探针焊盘结构具有与切割锯缝通道相邻的金属裂纹阻挡条，并且通过电探针垫结构。

2. 发明授权

US08912076B2 Crack deflector structure for improving semiconductor device robustness against saw-induced damage 有权
标题翻译：裂纹偏转器结构，用于提高半导体器件对锯损坏的鲁棒性
公开(公告)号：US08912076B2
公开(公告)日：2014-12-16
申请号：US12613175
申请日：2009-11-05
申请人： Jeffrey Alan West , Thomas D. Bonifield , Basab Chatterjee
发明人： Jeffrey Alan West , Thomas D. Bonifield , Basab Chatterjee
IPC分类号： H01L23/58 , H01L23/00
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
摘要翻译：一种集成电路，其包含将集成电路的内部区域与紧邻集成电路外部的划片线分隔开的裂纹偏转划线密封件及其形成方法。裂纹偏转划线密封件包括连续金属层和连续金属层之间的连续接触和连续通孔。连续金属层不延伸经过连续接触和连续通孔。连续接触和连续的通孔从划线密封的划线侧的下面的连续金属层的边缘凹陷，在划线密封件上提供成角度的外表面，其可以期望地终止裂纹扩展或将裂纹传播向上偏转到顶部表面划线或裂纹偏转划痕。

3. 发明授权

US07598507B2 Adjustable lithography blocking device and method 有权
标题翻译：可调光刻阻挡装置及方法
公开(公告)号：US07598507B2
公开(公告)日：2009-10-06
申请号：US10459681
申请日：2003-06-11
申请人： Basab Chatterjee , Richard L. Guldi , Keith W. Melcher
发明人： Basab Chatterjee , Richard L. Guldi , Keith W. Melcher
IPC分类号： G03B27/52 , G03B27/42 , G03B27/58
CPC分类号： G03F7/70066 , G03F7/70216 , G03F7/7035
摘要： The present invention provides, in one embodiment, a method (100) of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a resist located on a substrate (110). A radiation path through the reticle and a window assembly located between a radiation source and resist (120), is considered. It is determined whether or not the radiation would expose a predefined blocking area of the resist within the exposure zone (130). If the radiation would expose a blocking area, then the window assembly is configured to prevent radiation from exposing the blocking area in the exposure zone (140). Other embodiments include a window assembly (300) and system (400) to facilitate manufacturing of the semiconductor device according to the method (100).
摘要翻译：本发明在一个实施例中提供了制造半导体器件的方法（100）。常规形成的掩模版位于位于基底（110）上的抗蚀剂上。考虑通过掩模版的辐射路径和位于辐射源和抗蚀剂（120）之间的窗口组件。确定辐射是否暴露在曝光区域（130）内的抗蚀剂的预定阻挡区域。如果辐射将暴露阻挡区域，则窗口组件被配置为防止辐射暴露曝光区域（140）中的阻挡区域。其他实施例包括根据方法（100）制造半导体器件的窗口组件（300）和系统（400）。

4. 发明授权

US07212607B1 X-ray confocal defect detection systems and methods 有权
标题翻译： X射线共焦缺陷检测系统及方法
公开(公告)号：US07212607B1
公开(公告)日：2007-05-01
申请号：US11346054
申请日：2006-02-02
申请人： Satyavolu Srinivas Papa Rao , Richard L. Guldi , Basab Chatterjee
发明人： Satyavolu Srinivas Papa Rao , Richard L. Guldi , Basab Chatterjee
IPC分类号： G01B15/06
CPC分类号： G01N23/18
摘要： An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of formed layers. The target portion is a selected layer or portion of the plurality of formed layers. At least a portion of the x-ray is transmitted through the semiconductor device as transmitted x-ray. The confocal component receives the transmitted x-ray and passes target x-ray intensity from the target portion of the transmitted x-ray energy. Detectors receive the target x-ray from the confocal component from which defect analysis can be performed.
摘要翻译： x射线共焦缺陷检测系统包括x射线源，共焦分量和缺陷检测器，并在半导体器件的目标部分上操作。 x射线源产生x射线能量。半导体器件包括多个形成的层。目标部分是所选择的层或多个成形层的一部分。 X射线的至少一部分透射通过半导体器件作为透射的x射线。共聚焦组件接收透射的X射线，并从所传输的x射线能量的目标部分传递目标x射线强度。检测器从可以进行缺陷分析的共聚焦组件接收目标X射线。

5. 发明授权

US08273523B2 By-die-exposure for patterning of holes in edge die 有权
标题翻译：用于图案化边缘模具中的孔的逐模曝光
公开(公告)号：US08273523B2
公开(公告)日：2012-09-25
申请号：US11617130
申请日：2006-12-28
申请人： Shangting Detweiler , Basab Chatterjee , Chris D. Atkinson , Richard L. Guldi
发明人： Shangting Detweiler , Basab Chatterjee , Chris D. Atkinson , Richard L. Guldi
IPC分类号： G03F7/20
CPC分类号： H01L21/76816 , G03F7/70425 , G03F7/70625
摘要： In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor device can comprise forming a photoresist layer over a surface of a wafer, wherein the wafer comprises an edge that has a substantially rounded profile, an array of dies, and at least one edge die. The method can also comprise dividing a shot area into a plurality of shot portions and assigning a blind ID to each of the plurality of shot portions. The method can further comprise identifying one or more edge shot portions on the edge of the wafer for additional exposure; and exposing one or more times identified one or more edge shot portions on the edge of the wafer and blocking non-identified one or more non-edge shot portions.
摘要翻译：根据本发明，存在制造半导体器件和孔的半导体器件和方法。制造半导体器件的方法可以包括在晶片的表面上形成光致抗蚀剂层，其中晶片包括具有基本圆形轮廓的边缘，模具阵列和至少一个边缘模具。该方法还可以包括将拍摄区域分成多个拍摄部分，并将多个拍摄部分中的每一个分配盲ID。该方法还可以包括识别晶片边缘上的一个或多个边缘照射部分用于附加曝光; 并且在晶片的边缘上暴露出一个或多个标识出的一个或多个边缘射出部分并且阻挡未识别的一个或多个非边缘射出部分。

6. 发明授权

US07727885B2 Reduction of punch-thru defects in damascene processing 有权
标题翻译：减少镶嵌加工中的穿孔缺陷
公开(公告)号：US07727885B2
公开(公告)日：2010-06-01
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译：制造半导体器件，同时减轻金属化层中的导电空隙形成。提供基板。第一电介质层形成在衬底上。在第一电介质层内形成导电沟槽。在第一介电层上形成蚀刻停止层。在蚀刻停止层上/上形成第二介电层。在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。抗蚀剂掩模通过灰过程去除。执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。采用附加的表面电荷还原技术。通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。

7. 发明申请

US20080160779A1 BY-DIE-EXPOSURE FOR PATTERNING OF HOLES IN EDGE DIE 有权
标题翻译：用于在边缘模具中嵌入孔的旁路曝光
公开(公告)号：US20080160779A1
公开(公告)日：2008-07-03
申请号：US11617130
申请日：2006-12-28
申请人： Shangting Detweiler , Basab Chatterjee , Chris D. Atkinson , Richard L. Guldi
发明人： Shangting Detweiler , Basab Chatterjee , Chris D. Atkinson , Richard L. Guldi
IPC分类号： H01L21/469
CPC分类号： H01L21/76816 , G03F7/70425 , G03F7/70625
摘要： In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor device can comprise forming a photoresist layer over a surface of a wafer, wherein the wafer comprises an edge that has a substantially rounded profile, an array of dies, and at least one edge die. The method can also comprise dividing a shot area into a plurality of shot portions and assigning a blind ID to each of the plurality of shot portions. The method can further comprise identifying one or more edge shot portions on the edge of the wafer for additional exposure; and exposing one or more times identified one or more edge shot portions on the edge of the wafer and blocking non-identified one or more non-edge shot portions.
摘要翻译：根据本发明，存在制造半导体器件和孔的半导体器件和方法。制造半导体器件的方法可以包括在晶片的表面上形成光致抗蚀剂层，其中晶片包括具有基本圆形轮廓的边缘，模具阵列和至少一个边缘模具。该方法还可以包括将拍摄区域分成多个拍摄部分，并将多个拍摄部分中的每一个分配盲ID。该方法还可以包括识别晶片边缘上的一个或多个边缘照射部分用于附加曝光; 并且在晶片的边缘上暴露出一个或多个标识出的一个或多个边缘射出部分并且阻挡未识别的一个或多个非边缘射出部分。

8. 发明授权

US5571339A Hydrogen passivated heteroepitaxial III-V photovoltaic devices grown on lattice-mismatched substrates, and process 失效
标题翻译：在晶格失配衬底上生长的氢钝化异质外延III-V光伏器件，以及工艺
公开(公告)号：US5571339A
公开(公告)日：1996-11-05
申请号：US422850
申请日：1995-04-17
申请人： Steven A. Ringel , Richard W. Hoffman, Jr. , Basab Chatterjee
发明人： Steven A. Ringel , Richard W. Hoffman, Jr. , Basab Chatterjee
IPC分类号： H01L31/18 , H01L31/068 , H01L31/0304
CPC分类号： H01L31/1864 , H01L31/1852 , H01L31/1868 , Y02E10/544 , Y02P70/521 , Y10S438/933
摘要： A hydrogen passivated photovoltaic device such as a solar cell comprises a lattice mismatched substrate such as Ge or Si, and a hydrogen passivated heteroepitaxial layer such as InP grown on the substrate. The hydrogen passivated heteroepitaxial III-V photovoltaic device is produced by exposing a sample of a heteroepitaxial III-V material grown on a lattice-mismatched substrate to reactive hydrogen species at elevated temperatures. Reactive hydrogen forms bonds with dangling bonds along dislocations defined in the sample. The electrical activity in the dislocations is passivated as a result of the hydrogenation process.
摘要翻译：诸如太阳能电池的氢钝化光伏器件包括诸如Ge或Si的晶格失配衬底和在衬底上生长的氢钝化异质外延层，例如InP。氢钝化异质外延III-V光伏器件通过将生长在晶格失配衬底上的异质外延III-V材料的样品暴露于升高的温度下的反应性氢物质来制备。活性氢与样品中定义的位错形成与悬挂键的键。由于氢化过程，位错中的电活性被钝化。

9. 发明申请

US20080057711A1 Reduction of punch-thru defects in damascene processing 有权
标题翻译：减少镶嵌加工中的穿孔缺陷
公开(公告)号：US20080057711A1
公开(公告)日：2008-03-06
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译：制造半导体器件，同时减轻金属化层中的导电空隙形成。提供基板。第一电介质层形成在衬底上。在第一电介质层内形成导电沟槽。在第一介电层上形成蚀刻停止层。在蚀刻停止层上/上形成第二介电层。在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。抗蚀剂掩模通过灰过程去除。执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。采用附加的表面电荷还原技术。通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。

10. 发明申请

US20050040046A1 System for in situ seed layer remediation 审中-公开
标题翻译：原位种子层修复系统
公开(公告)号：US20050040046A1
公开(公告)日：2005-02-24
申请号：US10645975
申请日：2003-08-22
申请人： Aaron Frank , David Gonzalez , Basab Chatterjee , Richard Guldi
发明人： Aaron Frank , David Gonzalez , Basab Chatterjee , Richard Guldi
IPC分类号： C25D5/34 , C25D7/12 , H01L21/288 , H01L21/768 , C25D5/02
CPC分类号： H01L21/76843 , C25D5/34 , C25D7/123 , H01L21/2885 , H01L21/76838 , H01L21/76862 , H01L21/76874
摘要： The present invention provides a system for removing surface contaminants from a copper seed layer disposed upon a semiconductor substrate (210), in preparation for electrochemical deposition. An electrochemical deposition apparatus (202) is provided, having a contaminant remediation module (204) housed within. The semiconductor substrate (210) is transferred into the remediation module (204), where it is exposed in a reactive remediation system (216). Contaminants are removed from the surface of the copper seed layer, followed by an immediate transfer (212) of the substrate (210) from the remediation module (204) into a plating system (208) also housed within the electrochemical deposition apparatus (202).
摘要翻译：本发明提供一种用于从布置在半导体衬底（210）上的铜籽晶层去除表面污染物的系统，用于制备电化学沉积。提供了一种电化学沉积设备（202），其具有容纳在其内的污染物修复模块（204）。半导体衬底（210）被传送到修复模块（204）中，其中它暴露在反应性修复系统（216）中。从铜籽晶层的表面除去污染物，然后将基板（210）从修复模块（204）立即转移（212）到也容纳在电化学沉积装置（202）内的电镀系统（208）。

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