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1. 发明授权

US6149974A Method for elimination of TEOS/ozone silicon oxide surface sensitivity 失效
标题翻译：消除TEOS /臭氧氧化硅表面灵敏度的方法
公开(公告)号：US6149974A
公开(公告)日：2000-11-21
申请号：US851830
申请日：1997-05-05
申请人： Bang C. Nguyen , Shankar Vankataranan , Ruby Liao , Peter W. Lee
发明人： Bang C. Nguyen , Shankar Vankataranan , Ruby Liao , Peter W. Lee
IPC分类号： H01L21/31 , C23C16/02 , C23C16/40 , C23C16/44 , C23C16/455 , H01L21/316
CPC分类号： H01L21/02271 , C23C16/0272 , C23C16/402 , C23C16/45557 , H01L21/02164 , H01L21/02304 , H01L21/31612
摘要： A method and apparatus for reducing surface sensitivity of a TEOS/O.sub.3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.
摘要翻译：一种用于降低在衬底上形成的TEOS / O 3 SACVD氧化硅层的表面灵敏度的方法和装置，其沉积斜坡层，同时将压力升高到目标沉积压力，并在斜坡层上沉积SACVD层。在一个实施例中，在压力升高期间停止臭氧流以控制斜坡层的厚度。

2. 发明授权

US06319324B1 Method and apparatus for elimination of TEOS/ozone silicon oxide surface sensitivity 失效
标题翻译：消除TEOS /臭氧氧化硅表面灵敏度的方法和装置
公开(公告)号：US06319324B1
公开(公告)日：2001-11-20
申请号：US09662248
申请日：2000-09-14
申请人： Bang C. Nguyen , Shankar Vankataranan , Ruby Liao , Peter W. Lee
发明人： Bang C. Nguyen , Shankar Vankataranan , Ruby Liao , Peter W. Lee
IPC分类号： C23C1600
CPC分类号： H01L21/02271 , C23C16/0272 , C23C16/402 , C23C16/45557 , H01L21/02164 , H01L21/02304 , H01L21/31612
摘要： A method and apparatus for reducing surface sensitivity of a TEOS/O3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.
摘要翻译：一种用于降低在衬底上形成的TEOS / O 3 SACVD氧化硅层的表面灵敏度的方法和装置，其沉积斜坡层，同时将压力升高到目标沉积压力，并在斜坡层上沉积SACVD层。在一个实施例中，在压力升高期间停止臭氧流以控制斜坡层的厚度。

3. 发明授权

US5958510A Method and apparatus for forming a thin polymer layer on an integrated circuit structure 失效
标题翻译：在集成电路结构上形成薄聚合物层的方法和装置
公开(公告)号：US5958510A
公开(公告)日：1999-09-28
申请号：US583888
申请日：1996-01-08
申请人： Visweswaren Sivaramakrishnam , Bang C. Nguyen , Gayathri Rao , Stuardo Robles , Gary L. Fong , Vicente Lim , Peter W. Lee
发明人： Visweswaren Sivaramakrishnam , Bang C. Nguyen , Gayathri Rao , Stuardo Robles , Gary L. Fong , Vicente Lim , Peter W. Lee
IPC分类号： B05D7/24 , C23C16/44 , C23C16/452 , H01L21/312 , C23C16/00
CPC分类号： B05D1/60 , C23C16/44 , C23C16/452 , H01L21/312
摘要： A method and apparatus are disclosed for forming thin polymer layers on semiconductor substrates. In one embodiment, the method and apparatus include the sublimation of stable dimer parylene material, the pyrolytic conversion of such gaseous dimer material into reactive monomers, and for the optional blending of the resulting gaseous parylene monomers with one or more polymerizable materials in gaseous form capable of copolymerizing with the parylene monomers to form a low dielectric constant polymerized parylene material. An apparatus is also disclosed which provides for the distribution of the polymerizable gases into the deposition chamber, for cooling the substrate down to a temperature at which the gases will condense to form a polymerized dielectric material, for heating the walls of the deposition chamber to inhibit formation and accumulation of polymerized residues thereon, and for recapturing unreacted monomeric vapors exiting the deposition chamber. An apparatus is further provided downstream of the deposition chamber to control both the flow rate or residence time of the reactive monomer in the deposition chamber as well as to control the pressure of the deposition chamber. Provision is further made for an electrical bias to permit the apparatus to function as a plasma etch chamber, for in situ plasma cleaning of the chamber between depositions, for enhancing cracking of polymerizable precursor material, for heating the walls of the chamber and for providing heat sufficient to prevent polymerization in the gas phase.
摘要翻译：公开了用于在半导体衬底上形成薄聚合物层的方法和装置。在一个实施方案中，该方法和装置包括稳定的二聚聚对二甲苯材料的升华，这种气态二聚体材料的热解转化为反应性单体，以及任选地将得到的气体聚对二甲苯单体与一种或多种气态形式的可聚合材料混合与聚对二甲苯单体共聚以形成低介电常数的聚对二甲苯聚合物。还公开了一种设备，其提供可聚合气体分布到沉积室中，用于将衬底冷却至气体冷凝以形成聚合电介质材料的温度，以加热沉积室的壁以抑制在其上聚合的残余物的形成和积累，以及用于重新捕获离开沉积室的未反应的单体蒸气。还在沉积室的下游设置一个装置，以控制反应性单体在沉积室中的流速或停留时间以及控制沉积室的压力。进一步提供电偏压以允许该装置用作等离子体蚀刻室，用于沉积之间的腔室的原位等离子体清洁，用于增强可聚合前体材料的裂化，用于加热室的壁并提供热量足以防止气相中的聚合。

4. 发明授权

US08996785B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
标题翻译：基于NAND的混合NVM设计，将NAND和NOR与1串口串行接口集成
公开(公告)号：US08996785B2
公开(公告)日：2015-03-31
申请号：US12807997
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00 , G11C16/32 , G11C16/04
CPC分类号： G11C16/32 , G11C16/0408
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

5. 发明授权

US08237212B2 Nonvolatile memory with a unified cell structure 有权
标题翻译：具有统一单元结构的非易失性存储器
公开(公告)号：US08237212B2
公开(公告)日：2012-08-07
申请号：US13072281
申请日：2011-03-25
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

6. 发明授权

US07915092B2 Nonvolatile memory with a unified cell structure 有权
标题翻译：具有统一单元结构的非易失性存储器
公开(公告)号：US07915092B2
公开(公告)日：2011-03-29
申请号：US12001647
申请日：2007-12-12
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

7. 发明申请

US20110072201A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中
公开(公告)号：US20110072201A1
公开(公告)日：2011-03-24
申请号：US12807997
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/02 , G11C16/06
CPC分类号： G11C16/32 , G11C16/0408
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

8. 发明申请

US20080247230A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：新颖的单片，组合非易失性存储器允许字节，页和块写入，在单元阵列中没有干扰和分割，使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US20080247230A1
公开(公告)日：2008-10-09
申请号：US11483241
申请日：2006-07-07
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/06 , H01L21/336
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

9. 发明授权

US07149120B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US07149120B2
公开(公告)日：2006-12-12
申请号：US11011304
申请日：2004-12-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

10. 发明授权

US06714457B1 Parallel channel programming scheme for MLC flash memory 有权
标题翻译：用于MLC闪存的并行通道编程方案
公开(公告)号：US06714457B1
公开(公告)日：2004-03-30
申请号：US10233642
申请日：2002-09-03
申请人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
发明人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C2211/5622
摘要： In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.
摘要翻译：在本发明中，使用通道编程操作并行地对多个MLC闪速存储器单元进行编程，通过向连接到待编程单元的位线向字线施加高正电压和正电压。与字线电压组合的正位线电压产生足以在预定量的时间内将所需Vt电平并行编程到每个单元中的沟道电压。使用高正字线电压打开正在编程的单元的通道，并消除潜在的击穿条件，带对隧道电流，沟道夹紧和空穴注入栅绝缘体，同时允许具有低功耗的小对称单元和更高的耐力周期。

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