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    • 5. 发明授权
    • Parallel channel programming scheme for MLC flash memory
    • 用于MLC闪存的并行通道编程方案
    • US06714457B1
    • 2004-03-30
    • US10233642
    • 2002-09-03
    • Fu-Chang HsuPeter W. LeeHsing-Ya Tsao
    • Fu-Chang HsuPeter W. LeeHsing-Ya Tsao
    • G11C1604
    • G11C16/0483G11C11/5628G11C16/12G11C2211/5622
    • In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.
    • 在本发明中,使用通道编程操作并行地对多个MLC闪速存储器单元进行编程,通过向连接到待编程单元的位线向字线施加高正电压和正电压。 与字线电压组合的正位线电压产生足以在预定量的时间内将所需Vt电平并行编程到每个单元中的沟道电压。 使用高正字线电压打开正在编程的单元的通道,并消除潜在的击穿条件,带对隧道电流,沟道夹紧和空穴注入栅绝缘体,同时允许具有低功耗的小对称单元 和更高的耐力周期。
    • 7. 发明授权
    • Flash memory array structure suitable for multiple simultaneous operations
    • 闪存阵列结构适用于多个同时操作
    • US06584034B1
    • 2003-06-24
    • US10131271
    • 2002-04-23
    • Fu-Chang HsuPeter W. LeeHsing-Ya Tsao
    • Fu-Chang HsuPeter W. LeeHsing-Ya Tsao
    • G11C800
    • G11C16/10G11C7/18G11C8/12G11C2216/22
    • In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.
    • 在本发明中公开了一种用于同时读和写操作的闪速存储器。 存储器被划分成多个扇区,每个扇区具有扇区解码器。 扇区解码器将多个主位线连接到每个存储器扇区内所包含的多个子位线。虽然可以使用包括2M解码器和分层式解码器的其他解码器,但是使用解码器来解释本发明。 存储器阵列可以由各种架构进行配置,包括NOR,OR,NAND,AND,Dual-String和DINOR。 存储器单元可以由包括ETOX,FLOTOX,EPROM,EEPROM,分离栅极和PMOS的各种阵列结构形成。