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1. 发明申请

US20130294161A1 LOW-VOLTAGE FAST-WRITE NVSRAM CELL 审中-公开
标题翻译：低电压快速写NVSRAM单元
公开(公告)号：US20130294161A1
公开(公告)日：2013-11-07
申请号：US13888134
申请日：2013-05-06
申请人： Peter Wung Lee , Hsing-Ya Tsao
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C11/005 , G11C16/0466
摘要： This invention discloses several embodiments of a low-voltage fast-write NVSRAM cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping SONOS or MONOS flash cell with improvement by adding a Bridge circuit. This Bridge circuit is preferably inserted between each LV 6T SRAM cell and each HV Flash cell that comprises one paired complementary Flash strings. The Flash strings can be made of either 2T or 3T Flash strings. The tradeoff of using either a 2T or a 3T Flash string is subject to the gate area penalty and required design specs. One improvement for adding the Bridge circuit into the NVSRAM cell is to ensure the data writing between Flash cell and SRAM cell with the same polarity and to allow the operation down to low 1.2V Vdd.
摘要翻译：本发明公开了由2-多浮选栅型闪存单元或1-多电荷俘获SONOS或MONOS闪存单元中的任何一个制成的低电压快速写入NVSRAM单元的几个实施例，通过添加桥接电路。该桥电路优选地插入在每个LV 6T SRAM单元和包括一对互补闪存串的每个HV闪存单元之间。 Flash字符串可以由2T或3T Flash字符串组成。使用2T或3T闪存串的权衡取决于门区的罚款和所需的设计规格。将Bridge电路添加到NVSRAM单元中的一个改进是确保闪存单元和SRAM单元之间的数据写入相同的极性，并允许操作降低到1.2V Vdd。

2. 发明授权

US08295087B2 Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS 失效
标题翻译：行解码器和选择栅极解码器结构，适用于低于+/- 10v BVDS的基于闪存的EEPROM
公开(公告)号：US08295087B2
公开(公告)日：2012-10-23
申请号：US12456354
申请日：2009-06-16
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C11/4193
CPC分类号： G11C16/12 , G11C16/08 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.
摘要翻译：非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管非易失性存储单元。产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

3. 发明授权

US07636252B2 Nonvolatile memory with a unified cell structure 有权
标题翻译：具有统一单元结构的非易失性存储器
公开(公告)号：US07636252B2
公开(公告)日：2009-12-22
申请号：US11483241
申请日：2006-07-07
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

4. 发明申请

US20090310411A1 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS 失效
标题翻译：行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
公开(公告)号：US20090310411A1
公开(公告)日：2009-12-17
申请号：US12455936
申请日：2009-06-09
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C7/00 , G11C16/16 , G11C16/06 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0416 , G11C16/08 , G11C16/12 , G11C16/16
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

5. 发明申请

US20090279360A1 NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS或闪速存储器阵列，以及形成基于NAND的NMOS NOR闪存阵列
公开(公告)号：US20090279360A1
公开(公告)日：2009-11-12
申请号：US12387771
申请日：2009-05-07
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C16/06 , H01L21/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR闪存非易失性存储器电路阵列。每个NOR非易失性存储器电路包括以NAND串串联连接的多个电荷保持晶体管。最高电荷保持晶体管的漏极连接到与串联连接的电荷保持晶体管相关联的位线，并且最下面的电荷保持晶体管的源极连接到与电荷保持晶体管相关联的源极线。每行上的电荷保持晶体管的每个控制栅极共同连接到字线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

6. 发明授权

US07349257B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
标题翻译：组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作
公开(公告)号：US07349257B2
公开(公告)日：2008-03-25
申请号：US11633334
申请日：2006-12-04
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
摘要翻译：描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。闪存单元被块擦除时，EEPROM单元被字节擦除。小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

7. 发明授权

US07339824B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US07339824B2
公开(公告)日：2008-03-04
申请号：US11633326
申请日：2006-12-04
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

8. 发明授权

US07324384B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07324384B2
公开(公告)日：2008-01-29
申请号：US11442379
申请日：2006-05-26
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/06
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

9. 发明授权

US07283401B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 失效
标题翻译：单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案
公开(公告)号：US07283401B2
公开(公告)日：2007-10-16
申请号：US11391507
申请日：2006-03-28
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , G11C5/06 , H01L29/76 , H01L23/544
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
摘要翻译：非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

10. 发明申请

US20070133341A1 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
标题翻译：组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作
公开(公告)号：US20070133341A1
公开(公告)日：2007-06-14
申请号：US11633334
申请日：2006-12-04
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C7/10
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
摘要翻译：描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。闪存单元被块擦除时，EEPROM单元被字节擦除。小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

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