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1. 发明授权

US07928792B2 Apparatus for outputting complementary signals using bootstrapping technology 有权
标题翻译：使用自举技术输出互补信号的装置
公开(公告)号：US07928792B2
公开(公告)日：2011-04-19
申请号：US12367398
申请日：2009-02-06
申请人： Bai-Sun Kong , Byung-Hwa Jung , Sung-Chan Kang
发明人： Bai-Sun Kong , Byung-Hwa Jung , Sung-Chan Kang
IPC分类号： H03L5/00
CPC分类号： H03K19/01735
摘要： Disclosed herein is an apparatus for outputting complementary signals using bootstrapping technology. The apparatus for outputting complementary signals includes a precharaged logic block, one or more output nodes, and a bootstrapping circuit block. The precharged differential logic block generates a differential signal depending on an input signal. The one or more output nodes output the complementary signals depending on the differential signal. The bootstrapping circuit block is shared by the one or more output nodes, and amplifies the complementary signals.
摘要翻译：本文公开了一种使用自举技术输出互补信号的装置。用于输出互补信号的装置包括预先存储的逻辑块，一个或多个输出节点和自举电路块。预充电差分逻辑块根据输入信号产生差分信号。一个或多个输出节点根据差分信号输出互补信号。自举电路块由一个或多个输出节点共享，并放大互补信号。

2. 发明申请

US20080024183A1 Flip-flops and electronic digital circuits including the same 有权
标题翻译：触发器和包括其的电子数字电路
公开(公告)号：US20080024183A1
公开(公告)日：2008-01-31
申请号：US11819388
申请日：2007-06-27
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K3/0233
CPC分类号： H03K3/356121 , H03K3/356147 , H03K3/356191
摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.
摘要翻译：触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平在第一和第二输出信号进入第一级之后。当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

3. 发明授权

US6028453A Charge recycling differential logic (CRDL) circuit having true single-phase clocking scheme 失效
标题翻译：充电回收差分逻辑（CRDL）电路具有真正的单相时钟方案
公开(公告)号：US6028453A
公开(公告)日：2000-02-22
申请号：US950973
申请日：1997-10-15
申请人： Bai-Sun Kong
发明人： Bai-Sun Kong
IPC分类号： H03K19/20 , G06F1/28 , G06F7/50 , G06F7/507 , G11C11/412 , H03K19/00 , H03K19/096 , H03K19/173 , H03K19/21 , H03K19/094
CPC分类号： G06F7/507 , G06F7/501 , G06F7/503 , G06F7/505 , G11C11/412 , H03K19/0019 , H03K19/0963 , H03K19/1738 , H03K19/215 , G06F2207/3872 , G06F2207/3884
摘要： A novel logic family, called Charge Recycling Differential Logic (CRDL) circuit, reduces power consumption by utilizing a charge recycling technique and has a speed comparable to those of conventional dynamic logic circuits. The CRDL circuit also has improved noise margin due to inherently static operation. An 8-bit Manchester carry chain and full adders were fabricated using a 0.8 .mu.m single-poly double-metal n-well CMOS technology. The measurement results indicate about 16-48% improvements in power-delay product are obtained compared with Differential Cascode Voltage Switch (DCVS) circuit. Further, a circuit operating under a true single-phase clock signal includes a plurality of pipelined stages having a plurality of function blocks to implement a prescribed function. The function blocks are implemented using the novel CRDL circuit. An adder based on the CRDL circuit provided improved performance and reduced power consumption compared to an adder based on the DCVS circuit.
摘要翻译：称为电荷回收差分逻辑（CRDL）电路的新型逻辑系列通过利用电荷回收技术降低功耗，并且具有与常规动态逻辑电路相当的速度。由于固有的静态操作，CRDL电路还具有改善的噪声容限。使用0.8μm单多晶双金属n阱CMOS技术制造了8位曼彻斯特携带链和全加法器。测量结果表明，与差分串联电压开关（DCVS）电路相比，获得了功率延迟产品的16-48％的改进。此外，在真正的单相时钟信号下工作的电路包括具有多个功能块的多个流水线级，以实现规定的功能。功能块使用新颖的CRDL电路实现。与基于DCVS电路的加法器相比，基于CRDL电路的加法器提供了改进的性能和降低的功耗。

4. 发明授权

US07528630B2 High speed flip-flop 失效
标题翻译：高速触发器
公开(公告)号：US07528630B2
公开(公告)日：2009-05-05
申请号：US11970629
申请日：2008-01-08
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K19/00
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.
摘要翻译：触发器电路包括：预充电电路，其响应于第一脉冲信号对第一电路节点进行预充电;以及估计电路，其接收输入信号和第二脉冲信号。在激活第二脉冲信号时，估计电路响应于输入信号从第一节点放电电压。第一脉冲信号与时钟信号同步，第二脉冲信号从第一脉冲信号延迟。

5. 发明授权

US07504871B2 Flip-flops and electronic digital circuits including the same 有权
标题翻译：触发器和包括其的电子数字电路
公开(公告)号：US07504871B2
公开(公告)日：2009-03-17
申请号：US11819388
申请日：2007-06-27
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K3/00
CPC分类号： H03K3/356121 , H03K3/356147 , H03K3/356191
摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.
摘要翻译：触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平在第一和第二输出信号进入第一级之后。当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

6. 发明授权

US6163193A Self-timed latch circuit for high-speed very large scale integration (VLSI) 有权
标题翻译：用于高速非常大规模集成（VLSI）的自定时锁存电路
公开(公告)号：US6163193A
公开(公告)日：2000-12-19
申请号：US217201
申请日：1998-12-22
申请人： Bai-Sun Kong
发明人： Bai-Sun Kong
IPC分类号： H03K3/012 , H03K3/356 , H03K3/037
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/356182
摘要： A self-timed latch circuit according to the present invention includes a first inverter for inverting a set signal, a second inverter for inverting a reset signal, a first main driver driven by an output signal from the second inverter and the set signal, a second main driver driven by an output signal from the first inverter and the reset signal and a static latch cross-coupled with first and second output terminals of the first and second main drivers. The self-timed latch circuit according to the present invention reduces the power consumption and increases the operation speed of the circuit by removing a back-to-back connection and a serial connection of transistors applied to the conventional art. Further, since the static latch consists of cross-coupled inverters, the self-timed latch circuit according to the present invention prevents signal fighting during the logic transition of output signals and also reduces a leakage current generated during the operation of the circuit.
摘要翻译：根据本发明的自定时锁存电路包括用于反转设置信号的第一反相器，用于反转复位信号的第二反相器，由来自第二反相器的输出信号驱动的第一主驱动器和设定信号，第二反相器由第一反相器的输出信号和复位信号驱动的主驱动器和与第一和第二主驱动器的第一和第二输出端交叉耦合的静态锁存器。根据本发明的自定时锁存电路通过去除应用于传统技术的晶体管的背靠背连接和串联连接来降低功耗并增加电路的操作速度。此外，由于静态锁存器由交叉耦合的反相器组成，所以根据本发明的自定时锁存电路防止在输出信号的逻辑转换期间的信号消除，并且还减少在电路操作期间产生的漏电流。

7. 发明授权

US5903169A Charge recycling differential logic (CRDL) circuit and storage elements and devices using the same 失效
标题翻译：电荷回收差分逻辑（CRDL）电路和存储元件及使用其的器件
公开(公告)号：US5903169A
公开(公告)日：1999-05-11
申请号：US775951
申请日：1997-01-03
申请人： Bai-Sun Kong
发明人： Bai-Sun Kong
IPC分类号： G11C11/41 , G11C7/00 , G11C11/412 , H03K3/356 , H03K19/00 , H03K19/0944 , H03K19/096 , H03K19/173 , H03K19/21
CPC分类号： G11C11/412 , H03K19/0019 , H03K19/0963 , H03K19/1738 , H03K19/215 , H03K3/356147 , G06F2207/3884
摘要： A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.
摘要翻译：根据优选实施例的用于半导体器件的存储元件表现出较小的噪声并且以更快的速度消耗更少的功率。当输入电极的输入信号从（i）第一信号电平之一转换到第二信号电平时，第一电路将先前状态的第一存储节点维持在相同的信号电平，以及（ii）第三信号电平转换到第二信号电平。第一电路包括耦合到输入电极的第一多个晶体管，以及耦合到所述第一多个晶体管并在第一存储节点处彼此耦合的第一对晶体管。当所述输入信号从所述第二信号电平转换到所述第一信号电平时，耦合到所述第一电路的第二电路将所述第一存储节点的状态改变为（i）第一信号电平之一，以及（ii）第三信号电平，输入信号从第二信号电平转换到第三信号电平。

8. 发明申请

US20110304353A1 Scan Flip-Flop Circuits And Scan Test Circuits Including The Same 有权
标题翻译：扫描触发电路和包括其的扫描测试电路
公开(公告)号：US20110304353A1
公开(公告)日：2011-12-15
申请号：US13154731
申请日：2011-06-07
申请人： Hoi-Jin Lee , Bai-Sun Kong
发明人： Hoi-Jin Lee , Bai-Sun Kong
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K3/356182
摘要： A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.
摘要翻译：扫描触发器电路包括输入单元和输出单元。输入单元根据操作模式选择数据输入信号和扫描输入信号之一，并基于所选择的信号产生中间信号。输出单元基于中间信号产生输出信号，并根据操作模式选择数据输出端和扫描输出端之一，以通过所选择的输出端提供输出信号。所选择的输出端子处的电压电平在第一电压电平和第二电压电平之间双向转换。未选择的输出端子处的电压电平在第一电压电平和第二电压电平之间单向转变。

9. 发明授权

US07724073B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07724073B2
公开(公告)日：2010-05-25
申请号：US12287620
申请日：2008-10-10
申请人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
发明人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
IPC分类号： G05F3/02
CPC分类号： G11C5/145
摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.
摘要翻译：电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

10. 发明申请

US20080007338A1 Regulated cascode circuit, an amplifier including the same, and method of regulating a cascode circuit 有权
标题翻译：调节共源共栅电路，包括其的放大器以及调节共源共栅电路的方法
公开(公告)号：US20080007338A1
公开(公告)日：2008-01-10
申请号：US11799993
申请日：2007-05-03
申请人： Mu-Kyeng Jung , Jae-Whui Kim , Bai-Sun Kong
发明人： Mu-Kyeng Jung , Jae-Whui Kim , Bai-Sun Kong
IPC分类号： H03F3/16 , H03F3/45
CPC分类号： H03F1/223 , H03F3/45192 , H03F3/45632 , H03F2200/513 , H03F2203/45052 , H03F2203/45292 , H03F2203/45302 , H03F2203/45652
摘要： A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.
摘要翻译：调节共源共栅电路包括串联连接在接收第一电源电压的第一端子和输出端子之间的第一PMOS FET和第二PMOS FET，串联连接在输出端子和第一NMOS FET之间的第一NMOS FET和第二NMOS FET 接收第二电源电压的第二端子和调节电路。调节电路基于第一PMOS FET的漏极的电压输出用于将第一PMOS FET的漏极处的电压稳定到第二PMOS FET的栅极的第一控制信号，并输出用于稳定电压的第二控制信号基于第一NMOS FET的源极的电压，将第一NMOS FET的源极改变到第一NMOS FET的栅极。

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