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1. 发明申请

US20100026373A1 Semiconductor device for charge pumping 有权
标题翻译：用于电荷泵浦的半导体器件
公开(公告)号：US20100026373A1
公开(公告)日：2010-02-04
申请号：US12458533
申请日：2009-07-15
申请人： Joung-Yeal Kim , Young-hyun Jun , Bai-sun Kong
发明人： Joung-Yeal Kim , Young-hyun Jun , Bai-sun Kong
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.
摘要翻译：提供一种用于进行电荷泵送的半导体器件。半导体器件可以包括第一泵送单元，第二泵送单元和控制器。第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。控制器可以被配置为控制第一和第二泵送单元。第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。此外，传输单元可以被配置为控制升压电压的输出。

2. 发明授权

US08130028B2 CMOS charge pump with improved latch-up immunity 有权
标题翻译： CMOS电荷泵具有提高的闭锁抑制能力
公开(公告)号：US08130028B2
公开(公告)日：2012-03-06
申请号：US12691937
申请日：2010-01-22
申请人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
发明人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.
摘要翻译：提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

3. 发明申请

US20100207684A1 CMOS CHARGE PUMP WITH IMPROVED LATCH-UP IMMUNITY 有权
标题翻译： CMOS充电泵具有改进的放大功能
公开(公告)号：US20100207684A1
公开(公告)日：2010-08-19
申请号：US12691937
申请日：2010-01-22
申请人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
发明人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.
摘要翻译：提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

4. 发明申请

US20090134937A1 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US20090134937A1
公开(公告)日：2009-05-28
申请号：US12287620
申请日：2008-10-10
申请人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
发明人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
IPC分类号： G05F1/10
CPC分类号： G11C5/145
摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.
摘要翻译：电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

5. 发明授权

US07724073B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07724073B2
公开(公告)日：2010-05-25
申请号：US12287620
申请日：2008-10-10
申请人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
发明人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
IPC分类号： G05F3/02
CPC分类号： G11C5/145
摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.
摘要翻译：电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

6. 发明申请

US20110044121A1 SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER 审中-公开
标题翻译：具有用于控制位线负载的设备的半导体存储器件和提高位线感测放大器的感测效率
公开(公告)号：US20110044121A1
公开(公告)日：2011-02-24
申请号：US12860484
申请日：2010-08-20
申请人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
发明人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
IPC分类号： G11C7/06
CPC分类号： G11C11/4094 , G11C11/4091 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.
摘要翻译：半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器，读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块。

7. 发明申请

US20060077748A1 Address buffer circuit and method for controlling the same 失效
公开(公告)号：US20060077748A1
公开(公告)日：2006-04-13
申请号：US11232175
申请日：2005-09-21
申请人： Sung-Hoon Kim , Joung-Yeal Kim
发明人： Sung-Hoon Kim , Joung-Yeal Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

8. 发明授权

US07002852B2 Data output circuits for synchronous integrated circuit memory devices 失效
标题翻译：同步集成电路存储器件的数据输出电路
公开(公告)号：US07002852B2
公开(公告)日：2006-02-21
申请号：US10632439
申请日：2003-07-31
申请人： Chang-Man Khang , Joung-Yeal Kim
发明人： Chang-Man Khang , Joung-Yeal Kim
IPC分类号： G11C16/04
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.
摘要翻译：数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。多个寄存器输出选择开关的对通过相应的公共有效区域连接。第一数据组选择开关连接到多个寄存器输出选择开关的第一组的公共有效区。第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有效区域。输出驱动器连接到第一和第二数据组选择开关。

9. 发明授权

US07900176B2 Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same 失效
标题翻译：用于控制晶体管尺寸而不改变有源区的晶体管布局结构及其控制方法
公开(公告)号：US07900176B2
公开(公告)日：2011-03-01
申请号：US12000056
申请日：2007-12-07
申请人： Sung-Hoon Kim , Joung-Yeal Kim
发明人： Sung-Hoon Kim , Joung-Yeal Kim
IPC分类号： G06F17/50
CPC分类号： H01L27/088 , H01L27/0207
摘要： A structure for controlling the size of a transistor may include: an active region; a first gate line on the active region; one or more second gate lines on the active region; and source or drain regions arranged in three or more divided active regions that result from the first gate line and the one or more second gate lines dividing the active region into the divided active regions. A method of controlling the size of a transistor may include: arranging an active region; arranging a first gate line on the active region; arranging one or more second gate lines on the active region; arranging source or drain regions in three or more divided active regions; and controlling the size of the transistor by connecting to each other or separating from each other the source or drain regions using upper wires.
摘要翻译：用于控制晶体管尺寸的结构可以包括：有源区; 在活动区域上的第一个栅极线; 有源区上的一个或多个第二栅极线; 以及排列在三个或更多个分割的有源区域中的源极或漏极区域，其由第一栅极线和一个或多个第二栅极线分成有源区域分成有效区域。控制晶体管尺寸的方法可以包括：布置有源区; 在活动区域上布置第一栅极线; 在所述有源区上布置一个或多个第二栅极线; 在三个或更多个分割的活性区域中排列源区或漏区; 以及通过使用上部导线彼此连接或彼此分离源极或漏极区域来控制晶体管的尺寸。

10. 发明授权

US07643355B2 Semiconductor memory device and method of inputting/outputting data 有权
标题翻译：半导体存储器件及其输入/输出方法
公开(公告)号：US07643355B2
公开(公告)日：2010-01-05
申请号：US11896722
申请日：2007-09-05
申请人： Joung-Yeal Kim , Jeong-Don Lim , Sung-Hoon Kim , Woo-Jin Lee
发明人： Joung-Yeal Kim , Jeong-Don Lim , Sung-Hoon Kim , Woo-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C2207/107
摘要： According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.
摘要翻译：根据示例实施例，半导体存储器件可以包括存储器芯，输入电路和/或输出电路。输入电路可以被配置为使用响应于在不同周期期间启用的输入控制信号而工作的锁存电路从第一数据产生第二数据。输入电路还可以被配置为向存储器核提供第二数据。第二数据可以具有2N次第一数据的比特数，其中N是正整数。输出电路可以被配置为使用响应于在不同周期期间启用的输出控制信号而工作的锁存电路从第三数据生成第四数据。输出电路还可以被配置为向数据输出引脚提供第四数据。第四数据可以具有第三数据的比特数的1/2N倍。还提供了一种输入/输出数据的方法。

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