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1. 发明授权

US07928002B2 Method of forming wiring layer of semiconductor device 有权
标题翻译：形成半导体器件布线层的方法
公开(公告)号：US07928002B2
公开(公告)日：2011-04-19
申请号：US12396632
申请日：2009-03-03
申请人： Mu-kyeng Jung , Sun-jung Lee , Ki-chul Park
发明人： Mu-kyeng Jung , Sun-jung Lee , Ki-chul Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76816 , H01L21/76877 , H01L23/485 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.
摘要翻译：一种形成半导体器件的布线层的方法，包括形成第一层间绝缘层，以具有对应于待形成在支撑层上的层间绝缘层的厚度的一部分的第一厚度并形成第一接触插入第一层间绝缘层。该方法还包括在第一接触插塞和第一层间绝缘层上形成具有第二厚度的第二层间绝缘层，从而形成层间绝缘层，其中第二厚度对应于层间绝缘层的其余厚度并且形成与所述第二层间绝缘层中的所述第一接触插塞连接的第二接触插塞，由此形成包括所述第一接触插塞和所述第二接触插塞的局部布线层。

2. 发明申请

US20090227101A1 METHOD OF FORMING WIRING LAYER OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件接线层的方法
公开(公告)号：US20090227101A1
公开(公告)日：2009-09-10
申请号：US12396632
申请日：2009-03-03
申请人： Mu-kyeng JUNG , Sun-jung LEE , Ki-chul PARK
发明人： Mu-kyeng JUNG , Sun-jung LEE , Ki-chul PARK
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76895 , H01L21/76816 , H01L21/76877 , H01L23/485 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.
摘要翻译：一种形成半导体器件的布线层的方法，包括形成第一层间绝缘层，以具有对应于待形成在支撑层上的层间绝缘层的厚度的一部分的第一厚度并形成第一接触插入第一层间绝缘层。该方法还包括在第一接触插塞和第一层间绝缘层上形成具有第二厚度的第二层间绝缘层，从而形成层间绝缘层，其中第二厚度对应于层间绝缘层的其余厚度并且形成与所述第二层间绝缘层中的所述第一接触插塞连接的第二接触插塞，由此形成包括所述第一接触插塞和所述第二接触插塞的局部布线层。

3. 发明授权

US07560332B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07560332B2
公开(公告)日：2009-07-14
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
发明人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

4. 发明授权

US07285831B2 CMOS device with improved performance and method of fabricating the same 失效
标题翻译：具有改进性能的CMOS器件及其制造方法
公开(公告)号：US07285831B2
公开(公告)日：2007-10-23
申请号：US11179434
申请日：2005-07-12
申请人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
发明人： Mu-kyeng Jung , Hee-sung Kang , Hyuk-ju Ryu , Woo-young Chung , Kyung-soo Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/7846 , H01L21/823814 , H01L21/82385 , H01L29/7833 , H01L29/7843
摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.
摘要翻译：具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

5. 发明申请

US20060240636A1 Trench isolation methods of semiconductor device 审中-公开
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US20060240636A1
公开(公告)日：2006-10-26
申请号：US11358454
申请日：2006-02-21
申请人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
发明人： Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/76224 , H01L21/823878
摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.
摘要翻译：在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。形成第一光致抗蚀剂图案以覆盖P-MOS区域并暴露N-MOS区域。使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。去除第一光致抗蚀剂图案。使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一掩模图案。然后形成填充沟槽的沟槽隔离层。

6. 发明授权

US07679123B2 Integrated circuit devices including a capacitor 有权
标题翻译：集成电路器件包括电容器
公开(公告)号：US07679123B2
公开(公告)日：2010-03-16
申请号：US11684865
申请日：2007-03-12
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

7. 发明申请

US20070184610A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 失效
公开(公告)号：US20070184610A1
公开(公告)日：2007-08-09
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

8. 发明授权

US07208791B2 Integrated circuit devices including a capacitor 有权
标题翻译：集成电路器件包括电容器
公开(公告)号：US07208791B2
公开(公告)日：2007-04-24
申请号：US11168126
申请日：2005-06-28
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L27/108
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

9. 发明申请

US20050247968A1 Integrated circuit devices including a capacitor 有权
标题翻译：集成电路器件包括电容器
公开(公告)号：US20050247968A1
公开(公告)日：2005-11-10
申请号：US11168126
申请日：2005-06-28
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/00 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/108
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

10. 发明授权

US06940114B2 Integrated circuit devices including a MIM capacitor 有权
标题翻译：集成电路器件包括MIM电容器
公开(公告)号：US06940114B2
公开(公告)日：2005-09-06
申请号：US10657490
申请日：2003-09-08
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/00 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/108
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括在集成电路衬底上的集成电路衬底和金属 - 绝缘体 - 金属（MIM）电容器的导电下电极层。电介质层位于下电极层上，MIM电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间电介质层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

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