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1. 发明授权

US06669524B2 Method of treating surface of face panel for image display 失效
标题翻译：用于图像显示的面板表面处理方法
公开(公告)号：US06669524B2
公开(公告)日：2003-12-30
申请号：US09813202
申请日：2001-03-20
申请人： Atsushi Suzuki , Masahiro Yamamura , Yasunori Miura
发明人： Atsushi Suzuki , Masahiro Yamamura , Yasunori Miura
IPC分类号： H01J2928
CPC分类号： H01J9/20 , H01J29/896 , H01J2209/012 , Y10T428/254
摘要： In a method of treating a surface of a face panel for an image display including forming a film on the surface using coating materials, the film is formed of at least two layers including a first layer formed by a spray coating method and a second layer formed by a spin coating method to be superposed on the first layer. Thus, a face plate having antireflection/antistatic effects and providing high-resolution images can be obtained with high efficiency.
摘要翻译：在一种处理用于图像显示面板的表面的方法中，包括使用涂层材料在表面上形成膜，该膜由至少两层形成，包括通过喷涂法形成的第一层和形成的第二层通过旋涂法叠加在第一层上。因此，可以高效率地获得具有抗反射/抗静电效果并提供高分辨率图像的面板。

2. 发明授权

US06856082B2 Cathode ray tube with panel provided with colored layer 失效
标题翻译：阴极射线管与面板配有彩色层
公开(公告)号：US06856082B2
公开(公告)日：2005-02-15
申请号：US09902972
申请日：2001-07-11
申请人： Atsushi Suzuki , Masahiro Yamamura , Yasunori Miura
发明人： Atsushi Suzuki , Masahiro Yamamura , Yasunori Miura
IPC分类号： C03C17/34 , H01J29/86 , H01J29/88 , H01J29/89 , H01J29/10
CPC分类号： H01J29/89
摘要： This is a cathode ray tube having a panel provided with a colored layer on an outer surface of a face portion, wherein an emission luminance ratio is 75% or higher in a lowest part relative to a highest part, and a diffuse reflectance ratio is 90% or higher in a lowest part relative to a highest part in an image display area of the face portion. Due to this configuration, a cathode ray tube with a natural appearance can be obtained in which a luminance difference or a contrast difference is not perceived in the entire area of the face portion.
摘要翻译：这是具有在面部的外表面上设置有着色层的面板的阴极射线管，其中相对于最高部分的最低部分的发光亮度比为75％以上，漫反射率为90 在相对于脸部的图像显示区域中的最高部分的最低部分中的％或更高。由于这种构造，可以获得在脸部的整个区域中不感觉到亮度差或对比度差异的具有自然外观的阴极射线管。

3. 发明授权

US09309123B2 Process for producing a carbon nanostructure 有权
标题翻译：生产碳纳米结构的方法
公开(公告)号：US09309123B2
公开(公告)日：2016-04-12
申请号：US12733771
申请日：2008-09-19
申请人： Takeshi Nagasaka , Masahiro Yamamura , Yoshito Watanabe , Masaki Kondo , Yoshikazu Nakayama
发明人： Takeshi Nagasaka , Masahiro Yamamura , Yoshito Watanabe , Masaki Kondo , Yoshikazu Nakayama
IPC分类号： C23C16/00 , C01B31/02 , B01J23/745 , B01J35/00 , B01J37/02 , B82Y30/00 , B82Y40/00
CPC分类号： C01B31/0233 , B01J23/745 , B01J35/002 , B01J37/0215 , B01J37/0219 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/20 , C01B2202/34
摘要： This invention provides a method for forming a catalyst layer for carbon nanostructure growth, which can eliminate the influence of water in a liquid for catalyst layer formation, can grow homogeneous and highly oriented carbon nanostructures over the whole area of a substrate and can realize mass production of the carbon nanostructures, and a liquid for catalyst layer formation for use in the method, and a process for producing carbon nanostructures using the catalyst layer formed by the method. The catalyst layer for use in the production of CNTs is formed by preparing a catalyst metal salt solution of a catalyst metal-containing metal compound (a catalyst metal salt) dispersed or dissolved in a solvent having an ample wettability towards the substrate and coating the catalyst metal salt solution onto the substrate to a form a thin film. The thin film is then heat treated to form a catalyst layer. The substrate with the dried catalyst layer formed thereon is introduced into a carbon nanostructure synthetic device, and CNTs are grown by a thermal CVD method.
摘要翻译：本发明提供一种用于形成碳纳米结构生长催化剂层的方法，其可以消除用于催化剂层形成的液体中的水的影响，可以在基材的整个区域上生长均匀且高度取向的碳纳米结构，并且可以实现批量生产的碳纳米结构体，以及用于该方法的催化剂层形成用液体，以及使用该方法形成的催化剂层制造碳纳米结构体的方法。用于生产CNT的催化剂层是通过制备分散或溶解在具有充分润湿性的溶剂中的含催化剂金属的金属化合物（催化剂金属盐）的催化剂金属盐溶液形成于底物上并涂覆催化剂金属盐溶液形成薄膜。然后将该薄膜热处理以形成催化剂层。将其上形成有干燥催化剂层的基板引入碳纳米结构合成装置中，并通过热CVD法生长CNT。

4. 发明授权

US5910010A Semiconductor integrated circuit device, and process and apparatus for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法和装置
公开(公告)号：US5910010A
公开(公告)日：1999-06-08
申请号：US732215
申请日：1997-02-18
申请人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa
发明人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa
IPC分类号： H01L21/56 , H01L21/98 , H01L23/495 , H01L25/065 , H01L21/52 , H01L21/58 , H01L21/60
CPC分类号： H01L24/06 , H01L21/565 , H01L23/4951 , H01L23/49575 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2225/06527 , H01L2225/06551 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01055 , H01L2924/01058 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/351
摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.
摘要翻译： PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部每一帧。然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。然后将树脂包装从模具部件中释放出来。

5. 发明授权

US5680066A Signal transition detector circuit 失效
标题翻译：信号转换检测电路
公开(公告)号：US5680066A
公开(公告)日：1997-10-21
申请号：US182699
申请日：1994-01-13
申请人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira Ide , Masahiro Yamamura , Hideaki Uchida
发明人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira Ide , Masahiro Yamamura , Hideaki Uchida
IPC分类号： G11C7/10 , G11C8/06 , G11C8/10 , G11C8/18 , H03K5/1534 , H03K19/0175 , H03K5/153 , G01R29/02 , H03K3/033
CPC分类号： G11C7/1057 , G11C7/1051 , G11C8/06 , G11C8/10 , G11C8/18 , H03K19/017518 , H03K5/1534
摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要翻译：一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

6. 发明授权

US5324982A Semiconductor memory device having bipolar transistor and structure to avoid soft error 失效
标题翻译：半导体存储器件具有双极晶体管和结构，以避免软错误
公开(公告)号：US5324982A
公开(公告)日：1994-06-28
申请号：US769680
申请日：1991-10-02
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/04 , H01L29/70
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

7. 发明授权

US06864559B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06864559B2
公开(公告)日：2005-03-08
申请号：US10377717
申请日：2003-03-04
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/00
CPC分类号： H01L27/0623 , H01L27/0214 , H01L27/0218 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

8. 发明授权

US5497023A Semiconductor memory device having separately biased wells for isolation 失效
标题翻译：半导体存储器件具有单独偏置的阱用于隔离
公开(公告)号：US5497023A
公开(公告)日：1996-03-05
申请号：US352238
申请日：1994-12-08
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikasu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikasu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

9. 发明授权

US4059808A Differential amplifier 失效
标题翻译：差分放大器
公开(公告)号：US4059808A
公开(公告)日：1977-11-22
申请号：US708046
申请日：1976-07-23
申请人： Yoshio Sakamoto , Masahiro Yamamura
发明人： Yoshio Sakamoto , Masahiro Yamamura
IPC分类号： H03F3/30 , H03F3/45 , H03G3/10
CPC分类号： H03F3/45479 , H03F3/3071 , H03F3/45 , H03F2203/45094
摘要： In a semiconductor differential amplifier comprising a differential pair of npn transistors having the emitters connected to the emitter of lateral transistors, the bases supplied with an input signal, and the collectors connected in common to one terminal of the voltage source so as to derive the output signal from the collector of the lateral transistor, the emitter voltage of each of the differential pair transistors is applied to the common base of the pnp lateral transistors through a constant voltage element consisting of a transistor or a diode. Therefore, the voltage applied between the base and the substrate of the lateral transistor is reduced and hence the tolerance to the reverse breakdown voltage is increased and simplification of the circuit structure becomes possible. Further, a sink current path is provided between the base of the pnp lateral transistor and the other terminal of the voltage source to allow a stabilized bias current to flow through the differential amplifier.
摘要翻译：在包括具有连接到横向晶体管的发射极的发射极的npn晶体管的差分对的半导体差分放大器中，基极被提供有输入信号，并且集电极共同连接到电压源的一个端子，以便导出输出来自横向晶体管的集电极的信号，通过由晶体管或二极管组成的恒定电压元件将差分对晶体管的发射极电压施加到pnp横向晶体管的公共基极。因此，施加在横向晶体管的基极和基板之间的电压降低，因此提高了对反向击穿电压的容限，并且可以简化电路结构。此外，在pnp横向晶体管的基极和电压源的另一个端子之间设置一个电流通路，以允许稳定的偏置电流流过差分放大器。

10. 发明申请

US20100291297A1 METHOD FOR FORMING CATALYST LAYER FOR CARBON NANOSTRUCTURE GROWTH, LIQUID FOR CATALYST LAYER FORMATION, AND PROCESS FOR... 有权
标题翻译：用于碳纳米管生长的催化层的形成方法，用于催化层形成的液体和方法
公开(公告)号：US20100291297A1
公开(公告)日：2010-11-18
申请号：US12733771
申请日：2008-09-19
申请人： Takeshi Nagasaka , Masahiro Yamamura , Yoshito Watanabe , Masaki Kondo , Yoshikazu Nakayama
发明人： Takeshi Nagasaka , Masahiro Yamamura , Yoshito Watanabe , Masaki Kondo , Yoshikazu Nakayama
IPC分类号： C23C16/26 , B01J31/00
CPC分类号： C01B31/0233 , B01J23/745 , B01J35/002 , B01J37/0215 , B01J37/0219 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/20 , C01B2202/34
摘要： This invention provides a method for forming a catalyst layer for carbon nanostructure growth, which can eliminate the influence of water in a liquid for catalyst layer formation, can grow homogeneous and highly oriented carbon nanostructures over the whole area of a substrate and can realize mass production of the carbon nanostructures, and a liquid for catalyst layer formation for use in the method, and a process for producing carbon nanostructures using the catalyst layer formed by the method. The catalyst layer for use in the production of CNTs is formed by preparing a catalyst metal salt solution of a catalyst metal-containing metal compound (a catalyst metal salt) dispersed or dissolved in a solvent having an ample wettability towards the substrate and coating the catalyst metal salt solution onto the substrate to a form a thin film. The thin film is then heat treated to form a catalyst layer. The substrate with the dried catalyst layer formed thereon is introduced into a carbon nanostructure synthetic device, and CNTs are grown by a thermal CVD method.
摘要翻译：本发明提供一种用于形成碳纳米结构生长催化剂层的方法，其可以消除用于催化剂层形成的液体中的水的影响，可以在基材的整个区域上生长均匀且高度取向的碳纳米结构，并且可以实现批量生产的碳纳米结构体，以及用于该方法的催化剂层形成用液体，以及使用该方法形成的催化剂层制造碳纳米结构体的方法。用于生产CNT的催化剂层是通过制备分散或溶解在具有充分润湿性的溶剂中的含催化剂金属的金属化合物（催化剂金属盐）的催化剂金属盐溶液形成于底物上并涂覆催化剂金属盐溶液形成薄膜。然后将该薄膜热处理以形成催化剂层。将其上形成有干燥催化剂层的基板引入碳纳米结构合成装置中，并通过热CVD法生长CNT。

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