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1. 发明授权

US08802454B1 Methods of manufacturing a semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US08802454B1
公开(公告)日：2014-08-12
申请号：US13331702
申请日：2011-12-20
申请人： Arifur Rahman , Henley Liu , Cheang-Whang Chang , Myongseob Kim , Dong W. Kim
发明人： Arifur Rahman , Henley Liu , Cheang-Whang Chang , Myongseob Kim , Dong W. Kim
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/14
摘要： A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.
摘要翻译：提供了一种测试TSV的方法。在半导体衬底中形成多个TSV。布线层和第一接触阵列形成在基板的正面上。布线层将每个TSV耦合到第一接触阵列的相应触头。导电胶粘剂沉积在第一接触阵列上。导电粘合剂电耦合第一接触阵列的触点。载体用导电粘合剂粘合到基底的正面。在将载体接合到基板之后，将基板的背面变薄以使基板的背面上的每个TSV露出。形成第二接触阵列，其具有耦合到每个相应TSV的接触。通过测试第二接触阵列的触头之间的电导率来测试TSV，布线层和触点的电导率和连接。

2. 发明授权

US4134191A Method and apparatus to blow yarn and plug from high temperature yarn texturing jet device when yarn flow stops 失效
标题翻译：当纱线流动停止时，从高温纱线变形喷射装置吹纱和塞子的方法和装置
公开(公告)号：US4134191A
公开(公告)日：1979-01-16
申请号：US770123
申请日：1977-02-18
申请人： Dong W. Kim , Leonard J. Aberle
发明人： Dong W. Kim , Leonard J. Aberle
IPC分类号： D02G1/12 , D02G1/16 , D02H7/00
CPC分类号： D02G1/122
摘要： Apparatus and method are disclosed to prevent melted yarn when stopped in a high temperature texturing jet device utilizing high temperature fluid such as steam. The device of this invention is attached to the prior art texturing jet device. The attachment comprises a sleeve around the yarn ejector. The sleeve has at least two orifices communicating with a conduit for high pressure fluid having a valve actuated by a sensor to detect yarn stoppage. The high pressure fluid, such as air, blows the yarn plug and yarn from the texturing jet device. The method comprises sensing yarn stoppage with a sensor and actuating the valve in the high pressure fluid conduit communicating with at least two orifices in the sleeve surrounding at least the down stream portion of the injector and blowing any yarn in the texturing chamber out of the chamber with high pressure fluid.
摘要翻译：公开了一种装置和方法，用于在使用高温流体如蒸汽的高温纹理喷射装置停止时防止熔融纱线。本发明的装置附着在现有技术的纹理喷射装置上。附件包括围绕纱线喷射器的套筒。套管具有至少两个与用于高压流体的导管连通的孔，该孔具有由传感器致动的阀以检测纱线停止。诸如空气的高压流体从织纹喷射装置吹纱纱线和纱线。该方法包括用传感器检测纱线停止并且致动高压流体导管中的阀，其与套筒中至少两个孔连通，至少围绕喷射器的下游部分，并且将纹理室中的任何纱线吹出室外用高压液体。

3. 发明授权

US09236341B1 Through-silicon vias with metal system fill 有权
标题翻译：带有金属系统填充的硅通孔
公开(公告)号：US09236341B1
公开(公告)日：2016-01-12
申请号：US12868529
申请日：2010-08-25
申请人： Dong W. Kim , Myung-June Lee , Suresh Ramalingam
发明人： Dong W. Kim , Myung-June Lee , Suresh Ramalingam
IPC分类号： H01L23/58 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L2224/16225 , H01L2924/15311
摘要： A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.
摘要翻译：硅插入件包括形成在硅晶片部分上的多个图案化金属层和延伸穿过硅晶片部分的多个穿硅通孔。穿硅通孔具有相互扩散的导电元件。

4. 发明授权

US5393373A Methods of patterning and manufacturing semiconductor devices 失效
标题翻译：图案化和制造半导体器件的方法
公开(公告)号：US5393373A
公开(公告)日：1995-02-28
申请号：US135197
申请日：1993-10-12
申请人： Young K. Jun , Sa K. Ra , Dong W. Kim , Hyun H. Seo , Sung C. Kim , Jun K. Kim
发明人： Young K. Jun , Sa K. Ra , Dong W. Kim , Hyun H. Seo , Sung C. Kim , Jun K. Kim
IPC分类号： H01L21/02 , H01L21/033 , H01L21/8242 , H01L27/108 , H01L21/306 , B44C1/22
CPC分类号： H01L27/10817 , H01L21/0337 , H01L27/10852 , H01L28/92 , Y10S438/942
摘要： Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled. Where the present invention is applied to capacitors of semiconductor memory elements, the capacitor node surface area can be increased, depending on the etched back depth of a polysilicon layer.
摘要翻译：超精细图案化和制造半导体器件的方法。根据本发明的步骤包括在待蚀刻的层上涂覆具有山丘和谷的半球粒子层，该半球粒子层的蚀刻选择性高于第一层的蚀刻选择性，将半球粒子层的谷部填充到半球粒子层的谷部第二层具有比半球颗粒层的蚀刻选择性更高的蚀刻选择性，并且通过使用第二层作为掩模蚀刻半球粒子层的山丘以暴露第一层，并蚀刻第一层。由于半球颗粒层具有交替的山丘和山谷，可以实现约0.1μm的超精细图案化。由于可以控制半球层的平均尺寸和丘陵和山谷的密度，因此也可以控制图案尺寸。在将本发明应用于半导体存储器元件的电容器的情况下，可以根据多晶硅层的蚀刻回深度来增加电容器节点表面积。

5. 发明授权

US08519542B2 Air through-silicon via structure 有权
标题翻译：空气通过硅通孔结构
公开(公告)号：US08519542B2
公开(公告)日：2013-08-27
申请号：US12849181
申请日：2010-08-03
申请人： Namhoon Kim , Dong W. Kim , Paul Y. Wu
发明人： Namhoon Kim , Dong W. Kim , Paul Y. Wu
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/481 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.
摘要翻译：硅衬底具有从硅衬底的第一表面穿过硅衬底延伸到硅衬底的第二表面的导电通孔。电介质通孔从硅衬底的第二表面延伸到硅衬底的第一表面。

6. 发明授权

US07750466B2 Microelectronic assembly having second level interconnects including solder joints reinforced with crack arrester elements and method of forming same 失效
标题翻译：具有二级互连的微电子组件，其包括用裂纹避雷器元件加强的焊点以及其形成方法
公开(公告)号：US07750466B2
公开(公告)日：2010-07-06
申请号：US11852173
申请日：2007-09-07
申请人： Timothy P. Rothman , Leo J. Craft , Dong W. Kim
发明人： Timothy P. Rothman , Leo J. Craft , Dong W. Kim
IPC分类号： H01L23/485
CPC分类号： H01L23/42 , H01L23/10 , H01L23/3675 , H01L23/49816 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/16152 , H05K3/328 , H05K3/3436 , H05K3/4015 , H05K2201/0367 , Y02P70/613 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint.
摘要翻译：微电子组件和组装方法。微电子组件包括具有封装基板的封装，该封装基板具有管芯侧和载体侧，并且衬底位于其载体侧上; 在其芯片侧安装在封装基板上的微电子管芯; 以及将管芯与封装衬底电耦合的第一级互连阵列。组件还包括具有衬底侧的载体，该封装在衬底侧安装在载体上; 以及将所述封装电耦合到所述载体的第二级互连阵列，所述第二级互连件中的每一个包括将所述衬底焊盘连接到所述载体焊盘的焊接接头，以及至少部分地包围在所述焊接接头内的防裂器元件。

7. 发明授权

US5387531A Hole capacitor for dram cell and a fabrication method thereof 失效
标题翻译：电容器用孔电容器及其制造方法
公开(公告)号：US5387531A
公开(公告)日：1995-02-07
申请号：US942228
申请日：1992-09-09
申请人： Sa K. Rha , Dong W. Kim
发明人： Sa K. Rha , Dong W. Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L28/82 , H01L27/10808 , H01L28/84 , H01L28/86 , Y10S438/964
摘要： A method for making a hole capacitor for DRAM cell includes the steps of: depositing a nitride layer and a lower oxide layer, and forming a buried contact hole, after forming a MOS transistor upon a semiconductor substrate. Thereafter depositing an in-situ doped non-crystalline silicon layer, an undoped non-crystalline silicon layer, and a hemispherical polysilicon layer in all in sequence with a thickness of 1500 .ANG. or over. An upper oxide film is deposited, and then, carrying out an etch-back on the upper oxide film so that the hemispherical polysilicon domes are exposed. Etching the polysilicon layers using the remained portions of the upper oxide film remaining on the valleys of the hemispherical polysilicon as a mask, in order to form a plurality of holes perforated from the domes to the insulating layer located under the layers. The upper oxide film is removed through an etch process. Patterning a lower electrode of the capacitor, etching the lower oxide film, forming a dielectric layer on the surface of the lower electrode, and forming an upper electrode in match with the lower electrode across the dielectric layer.
摘要翻译：制造用于DRAM单元的空穴电容器的方法包括以下步骤：在半导体衬底上形成MOS晶体管之后，沉积氮化物层和低氧化物层，并形成掩埋接触孔。之后沉积原位掺杂的非晶硅层，未掺杂的非晶硅层和半球形多晶硅层，其厚度均为1500纳米或以上。沉积上氧化膜，然后在上氧化膜上进行回蚀，以使半球状多晶硅圆顶露出。使用保留在半球状多晶硅的谷部上的上部氧化膜的剩余部分作为掩模蚀刻多晶硅层，以便形成从圆顶穿孔到位于层下方的绝缘层的多个孔。通过蚀刻工艺去除上部氧化物膜。对电容器的下电极进行构图，蚀刻低氧化物膜，在下电极的表面上形成电介质层，并在电介质层上形成与下电极匹配的上电极。

8. 发明申请

US20120032326A1 AIR THROUGH-SILICON VIA STRUCTURE 有权
标题翻译：通过结构的空气通过硅
公开(公告)号：US20120032326A1
公开(公告)日：2012-02-09
申请号：US12849181
申请日：2010-08-03
申请人： Namhoon Kim , Dong W. Kim , Paul Y. Wu
发明人： Namhoon Kim , Dong W. Kim , Paul Y. Wu
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/481 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.
摘要翻译：硅衬底具有从硅衬底的第一表面穿过硅衬底延伸到硅衬底的第二表面的导电通孔。电介质通孔从硅衬底的第二表面延伸到硅衬底的第一表面。

9. 发明申请

US20090065943A1 Microelectronic Assembly Having Second Level Interconnects Including Solder Joints Reinforced with Crack Arrester Elements and Method of Forming Same 失效
标题翻译：具有二次互连的微电子组件，其中包括用裂纹避雷器元件加固的焊点及其形成方法
公开(公告)号：US20090065943A1
公开(公告)日：2009-03-12
申请号：US11852173
申请日：2007-09-07
申请人： Timothy P. Rothman , Leo J. Craft , Dong W. Kim
发明人： Timothy P. Rothman , Leo J. Craft , Dong W. Kim
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/42 , H01L23/10 , H01L23/3675 , H01L23/49816 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/16152 , H05K3/328 , H05K3/3436 , H05K3/4015 , H05K2201/0367 , Y02P70/613 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint.
摘要翻译：微电子组件和组装方法。微电子组件包括具有封装基板的封装，该封装基板具有管芯侧和载体侧，并且衬底位于其载体侧上; 在其芯片侧安装在封装基板上的微电子管芯; 以及将管芯与封装衬底电耦合的第一级互连阵列。组件还包括具有衬底侧的载体，该封装在衬底侧安装在载体上; 以及将所述封装电耦合到所述载体的第二级互连阵列，所述第二级互连件中的每一个包括将所述衬底焊盘连接到所述载体焊盘的焊接接头，以及至少部分地包围在所述焊接接头内的防裂器元件。

10. 发明授权

US5521408A Hole capacitor for DRAM cell 失效
标题翻译：用于DRAM单元的孔电容器
公开(公告)号：US5521408A
公开(公告)日：1996-05-28
申请号：US279022
申请日：1994-07-22
申请人： Sa K. Rha , Dong W. Kim
发明人： Sa K. Rha , Dong W. Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/76
CPC分类号： H01L28/82 , H01L27/10808 , H01L28/84 , H01L28/86 , Y10S438/964
摘要： A hole capacitor is formed which has a first electrode with a plurality of holes and projections. Another electrode is matched with the first electrode and separated from the first electrode by a dielectric layer. A method for making the hole capacitor includes the steps of: depositing a nitride layer and a lower oxide layer, and forming a buried contact hole, after forming an MOS transistor upon a semiconductor substrate. Thereafter depositing an in-situ doped non-single crystalline silicon layer, an undoped non-single crystalline silicon layer, and a hemispherical polysilicon layer in all in sequence with a thickness of 1500 .ANG. or over. An upper oxide film is deposited, and then, carrying out an etch-back on the upper oxide film so that the hemispherical polysilicon domes are exposed. Etching the polysilicon layers using the remaining portions of the upper oxide film remaining on the valleys of the hemispherical polysilicon as a mask, in order to form a plurality of holes perforated from the domes to the insulating layer located under the layers. The upper oxide film is removed through an etch process. Patterning a lower electrode of the capacitor, etching the lower oxide film, forming a dielectric layer on the surface of the lower electrode, and forming an upper electrode in match with the lower electrode across the dielectric layer.
摘要翻译：形成具有多个孔和突起的第一电极的空穴电容器。另一电极与第一电极匹配并且通过介电层与第一电极分离。一种制造孔电容器的方法包括以下步骤：在半导体衬底上形成MOS晶体管之后，沉积氮化物层和低氧化物层，并形成掩埋接触孔。之后，沉积原位掺杂的非单晶硅层，未掺杂的非单晶硅层和半球状多晶硅层，其厚度均为1500纳米或以上。沉积上氧化膜，然后在上氧化膜上进行回蚀，以使半球状多晶硅圆顶露出。使用保留在半球状多晶硅的谷部上的上部氧化物膜的剩余部分作为掩模蚀刻多晶硅层，以便形成从顶部穿孔到位于层下方的绝缘层的多个孔。通过蚀刻工艺去除上部氧化物膜。对电容器的下电极进行构图，蚀刻低氧化物膜，在下电极的表面上形成电介质层，并在电介质层上形成与下电极匹配的上电极。

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