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1. 发明授权

US09508563B2 Methods for flip chip stacking 有权
标题翻译：倒装芯片堆叠方法
公开(公告)号：US09508563B2
公开(公告)日：2016-11-29
申请号：US13548029
申请日：2012-07-12
申请人： Woon-Seong Kwon , Suresh Ramalingam
发明人： Woon-Seong Kwon , Suresh Ramalingam
IPC分类号： H01L21/48 , H01L23/14 , H01L23/498 , H01L23/00 , H01L25/065
CPC分类号： H01L21/4853 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/75744 , H01L2224/7598 , H01L2224/75983 , H01L2224/75987 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/014 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2224/81 , H01L2924/00014
摘要： A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.
摘要翻译：一种用于倒装芯片堆叠的方法包括：形成包括多个空腔的空腔晶片和一对角引导件，将具有耦合到腔晶片上的TSV插入器表面的焊料凸块放置穿通硅通孔（TSV）插入器，使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，将集成电路（IC）管芯放置在TSV插入器的另一表面上，使得IC管芯，TSV插入器并且焊料凸起形成堆叠的插入单元，从空腔晶片去除堆叠的中介层单元，并且将堆叠的插入单元的焊料凸块接合到有机基板，使得堆叠的插入单元和有机基板形成倒装芯片。

2. 发明授权

US09236341B1 Through-silicon vias with metal system fill 有权
标题翻译：带有金属系统填充的硅通孔
公开(公告)号：US09236341B1
公开(公告)日：2016-01-12
申请号：US12868529
申请日：2010-08-25
申请人： Dong W. Kim , Myung-June Lee , Suresh Ramalingam
发明人： Dong W. Kim , Myung-June Lee , Suresh Ramalingam
IPC分类号： H01L23/58 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L2224/16225 , H01L2924/15311
摘要： A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.
摘要翻译：硅插入件包括形成在硅晶片部分上的多个图案化金属层和延伸穿过硅晶片部分的多个穿硅通孔。穿硅通孔具有相互扩散的导电元件。

3. 再颁专利

USRE44629E1 Process for assembling an integrated circuit package having a substrate vent hole 有权
标题翻译：用于组装具有基板通气孔的集成电路封装的工艺
公开(公告)号：USRE44629E1
公开(公告)日：2013-12-10
申请号：US11001714
申请日：2004-11-30
申请人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
发明人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
IPC分类号： H01K3/10
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01077 , H01L2924/15151 , H01L2924/15311 , Y10T29/4913 , Y10T29/49146 , Y10T29/49163 , Y10T29/49165 , H01L2924/00 , H01L2224/0401
摘要： The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.
摘要翻译：本发明涉及一种提供集成电路封装的方法，所述集成电路封装具有带通气孔的基板。集成电路封装包括具有开口的基板和安装到基板的集成电路。在基板和集成电路之间分配底部填充材料。

4. 发明授权

US06490166B1 Integrated circuit package having a substrate vent hole 有权
标题翻译：具有基板通气孔的集成电路封装
公开(公告)号：US06490166B1
公开(公告)日：2002-12-03
申请号：US09330373
申请日：1999-06-11
申请人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
发明人： Suresh Ramalingam , Nagesh Vodrahalli , Michael J. Costello , Mun Leong Loke , Ravi V. Mahajan
IPC分类号： H01L2100
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01077 , H01L2924/15151 , H01L2924/15311 , Y10T29/4913 , Y10T29/49146 , Y10T29/49163 , Y10T29/49165 , H01L2924/00 , H01L2224/0401
摘要： The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.
摘要翻译：本发明涉及一种提供集成电路封装的方法，所述集成电路封装具有带通气孔的基板。集成电路封装包括具有开口的基板和安装到基板的集成电路。在基板和集成电路之间分配底部填充材料。

5. 发明授权

US06486440B1 Redundant package for optical components 有权
标题翻译：用于光学元件的冗余封装
公开(公告)号：US06486440B1
公开(公告)日：2002-11-26
申请号：US09901474
申请日：2001-07-09
申请人： Douglas E. Crafts , James F. Farrell , Mark B. Farrelly , Suresh Ramalingam
发明人： Douglas E. Crafts , James F. Farrell , Mark B. Farrelly , Suresh Ramalingam
IPC分类号： H05B100
CPC分类号： G02B6/30 , G02B6/1203 , G02B6/36
摘要： A redundant package for optical components includes an inner package enclosing the optical component, and an outer package enclosing the inner package. A heater may be disposed in the inner package proximate the optical component to control its temperature, and to maintain this temperature control, the outer package creates an isolated air pocket around the inner package which thermally insulates the inner package from the outside environment. The outer package is formed of a material having low thermal conductivity, to promote this insulating function. This package is especially useful if the optical component comprises a planar lightwave circuit (PLC), e.g., an arrayed waveguide grating (AWG), which requires tight temperature control and structural integrity to maintain the integrity of the optical paths.
摘要翻译：用于光学部件的冗余封装包括封装光学部件的内部封装以及封装内部封装的外部封装。加热器可以靠近光学部件设置在内部包装件中以控制其温度，并且为了保持该温度控制，外部包装围绕内部包装形成隔离的空气袋，其将内部包装与外部环境绝热。外包装由具有低导热性的材料形成，以促进该绝缘功能。如果光学组件包括平面光波电路（PLC），例如阵列波导光栅（AWG），则该封装是特别有用的，其需要严格的温度控制和结构完整性来维持光路的完整性。

6. 发明申请

US20140017852A1 METHODS FOR FLIP CHIP STACKING 有权
标题翻译： FLIP芯片堆叠方法
公开(公告)号：US20140017852A1
公开(公告)日：2014-01-16
申请号：US13548029
申请日：2012-07-12
申请人： Woon-Seong Kwon , Suresh Ramalingam
发明人： Woon-Seong Kwon , Suresh Ramalingam
IPC分类号： H01L21/98
CPC分类号： H01L21/4853 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/75744 , H01L2224/7598 , H01L2224/75983 , H01L2224/75987 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/014 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2224/81 , H01L2924/00014
摘要： A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.
摘要翻译：一种用于倒装芯片堆叠的方法包括：形成包括多个空腔的空腔晶片和一对角引导件，将具有耦合到腔晶片上的TSV插入器表面的焊料凸块放置穿通硅通孔（TSV）插入器，使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，将集成电路（IC）管芯放置在TSV插入器的另一表面上，使得IC管芯，TSV插入器并且焊料凸起形成堆叠的插入单元，从空腔晶片去除堆叠的中介层单元，并且将堆叠的插入单元的焊料凸块接合到有机基板，使得堆叠的插入单元和有机基板形成倒装芯片。

7. 发明申请

US20050109769A1 ELECTROMAGNETIC HEMMING MACHINE AND METHOD FOR JOINING SHEET METAL LAYERS 有权
标题翻译：电磁铆接机及接合板金属层的方法
公开(公告)号：US20050109769A1
公开(公告)日：2005-05-26
申请号：US10719583
申请日：2003-11-21
申请人： John McClure , Suresh Ramalingam , James Lezotte
发明人： John McClure , Suresh Ramalingam , James Lezotte
IPC分类号： B23K20/06 , B23K20/22 , H05B6/14 , H05B6/10
CPC分类号： B21D39/021 , B21D26/14 , B23K20/06 , B23K20/22 , B23K33/002 , B23K2103/04 , B23K2103/10
摘要： A hemming machine for joining an inner sheet metal panel with an outer sheet metal panel comprising: a hemming tool containing an electromagnetic coil positioned to electromagnetically crimp and/or weld the outer sheet metal panel to the inner sheet metal panel, where a backing die positioned outside the inner metallic sheet and the outer metallic sheet opposite the electromagnetic coil.
摘要翻译：一种用于将内部金属板与外部金属板接合的折边机，包括：折叠工具，其包含电磁线圈，该电磁线圈定位成将外部金属板电磁地卷曲和/或焊接到内部金属板，其中背衬模具定位在内部金属片外面和与电磁线圈相对的外部金属片。

8. 发明授权

US06778727B2 Optic switch 失效
公开(公告)号：US06778727B2
公开(公告)日：2004-08-17
申请号：US10714414
申请日：2003-11-14
申请人： Suresh Ramalingam , Venkatesan Murali
发明人： Suresh Ramalingam , Venkatesan Murali
IPC分类号： G02B626
CPC分类号： G02F1/3132 , G02F1/0147 , G02F1/3137
摘要： An apparatus comprising a body having dimensions suitable for light transmission therethrough, the body comprising a core extending therethrough, a first portion of the core comprising an index of refraction different than a second portion of the core and a cladding disposed about the core. An optical electronic integrated circuit (OEIC) substrate comprising a plurality of waveguides and a light source emitter coupled to at least one of the plurality of waveguides. A method comprising providing optical signals to an optical electronic integrated circuit (OEIC) through a plurality of waveguides are arranged in a circuit of different paths; and selecting an optical path by the index of refraction of a portion of the core.

9. 发明授权

US06606425B1 Transfer molded packages with embedded thermal insulation 有权
标题翻译：具有嵌入式保温的转移成型包装
公开(公告)号：US06606425B1
公开(公告)日：2003-08-12
申请号：US10100277
申请日：2002-03-18
申请人： Douglas E. Crafts , Kenzo Ishida , David J. Chapman , Duane Cook , James F. Farrell , Suresh Ramalingam , Steven M. Swain
发明人： Douglas E. Crafts , Kenzo Ishida , David J. Chapman , Duane Cook , James F. Farrell , Suresh Ramalingam , Steven M. Swain
IPC分类号： G02B612
CPC分类号： G02B6/12026 , G02B6/4253 , G02B6/4273
摘要： An optical component package, in which a transfer molded layer of material (e.g., syntactic foam in one embodiment) is formed at least partially around, or entirely around, the optical component to provide structural and thermal insulation around the component. The optical component may be a planar lightwave circuit (PLC), with a protective passivation layer formed between the PLC and the layer of syntactic foam, to de-couple stresses and thermal transfer between the PLC and the layer of syntactic foam. Strengthening caps, fiber assemblies, and a heater may be provided with the PLC assembly, around which the layer of syntactic foam can also be formed. The protective passivation layer can also be formed between these structures and the syntactic foam; in one embodiment between at least two strengthening caps formed on opposing edges of the PLC. The disclosed package provides numerous structural, thermal and size benefits.
摘要翻译：一种光学部件封装，其中材料的转移模制层（例如，一个实施例中的复合泡沫）至少部分地围绕或完全围绕光学部件形成，以在部件周围提供结构和隔热。光学部件可以是平面光波电路（PLC），在PLC和复合泡沫层之间形成保护钝化层，以解除PLC和复合泡沫层之间的应力和热传递。可以提供加强盖，纤维组件和加热器，PLC组件也可以形成层压泡沫层。保护钝化层也可以在这些结构和复合泡沫之间形成; 在一个实施例中，在形成在PLC的相对边缘上的至少两个加强盖之间。所公开的封装提供了许多结构，热和尺寸的优点。

10. 发明授权

US06238948B1 Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material 有权
标题翻译：控制崩溃芯片连接（C4）集成电路封装，具有密封底部填充材料的圆角
公开(公告)号：US06238948B1
公开(公告)日：2001-05-29
申请号：US09262131
申请日：1999-03-03
申请人： Suresh Ramalingam
发明人： Suresh Ramalingam
IPC分类号： H01L2144
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： A seal process step wherein a fillet material is dispensed on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may include an underfill material that is attached to the integrated circuit and the substrate and a fillet which seals the underfill material and the IC. The uniform seal created by the fillet material may inhibit cracking of the integrated circuit (die) during thermo-mechanical loading.
摘要翻译：一种密封工艺步骤，其中将圆角材料分配在集成电路封装上，该集成电路封装可以包括安装到衬底的集成电路。封装可以包括附着到集成电路和基板的底部填充材料以及密封底部填充材料和IC的圆角。由圆角材料产生的均匀密封可抑制热机械加载期间集成电路（模具）的开裂。

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