专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06977547B2 Minimizing changes in the amplification factor of an amplification circuit during operation 有权
标题翻译：最大限度地减少放大电路在放大电路中的变化
公开(公告)号：US06977547B2
公开(公告)日：2005-12-20
申请号：US10722409
申请日：2003-11-28
申请人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota
发明人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota
IPC分类号： H03F3/45
CPC分类号： H03F3/45977
摘要： A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification factor of an amplification circuit during operation.
摘要翻译：在放大器的输出端提供电阻器（或具有不改变的阻抗的部件），这使得放大电路在操作期间的放大系数的变化最小化。

2. 发明授权

US07088149B2 Enhancing SNR and throughput performance of integrated circuits 有权
标题翻译：提高集成电路的SNR和吞吐量性能
公开(公告)号：US07088149B2
公开(公告)日：2006-08-08
申请号：US10724517
申请日：2003-11-29
申请人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota , Shakti Shankar Rath , Gautam Salil Nandi , Vineet Mishra , Ravishankar S. Ayyagari , Nitin Agarwal
发明人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota , Shakti Shankar Rath , Gautam Salil Nandi , Vineet Mishra , Ravishankar S. Ayyagari , Nitin Agarwal
IPC分类号： G11C27/02
CPC分类号： H03F1/26 , H03F3/45188 , H03F3/45475 , H03F3/4565 , H03F3/45937 , H03F3/72
摘要： Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.
摘要翻译：低压晶体管用于高压环境。低电压晶体管可用于处理信号的路径以增加吞吐量性能。通过使用与高压环境相关联的高压电源，可以获得更高的信噪比。实施各种技术以确保低电压晶体管不被长时间暴露于高电压而损坏。

3. 发明授权

US07310058B2 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) 有权
标题翻译：减少将模拟输入采样转换为模拟数字转换器（ADC）中数字码的时间，
公开(公告)号：US07310058B2
公开(公告)日：2007-12-18
申请号：US11160859
申请日：2005-07-13
申请人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvaraya A. Pentakota , Sandeep Oswal
发明人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvaraya A. Pentakota , Sandeep Oswal
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

4. 发明授权

US07969334B2 Apparatus for correcting setting error in an MDAC amplifier 有权
标题翻译：用于校正MDAC放大器设置误差的装置
公开(公告)号：US07969334B2
公开(公告)日：2011-06-28
申请号：US12645220
申请日：2009-12-22
申请人： Ganesh Kiran , Visvesvaraya A. Pentakota
发明人： Ganesh Kiran , Visvesvaraya A. Pentakota
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/167 , H03M1/66
摘要： Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capacitor network that compensates for this settling error. Thus, a more accurate pipelined ADC can now be produced.
摘要翻译：通常在流水线模数转换器（ADC）中采用的乘法数字模拟转换器（MDAC）可能会产生与MDAC放大器相关的稳定误差。这里提供了一个电路，其中包括额外的放大器和补偿该稳定误差的电容器网络。因此，现在可以生产更精确的流水线ADC。

5. 发明申请

US20090135037A1 Correcting Offset Errors Associated With A Sub-ADC In Pipeline Analog To Digital Converters 有权
标题翻译：纠正与管道模拟数字转换器中的子ADC相关的偏移误差
公开(公告)号：US20090135037A1
公开(公告)日：2009-05-28
申请号：US11945278
申请日：2007-11-27
申请人： Nitin Agarwal , Ramesh Kumar Singh , Visvesvaraya A. Pentakota , Dantes John , Supreet Joshi
发明人： Nitin Agarwal , Ramesh Kumar Singh , Visvesvaraya A. Pentakota , Dantes John , Supreet Joshi
IPC分类号： H03M3/00
CPC分类号： H03M1/1023 , H03M1/0607 , H03M1/0624 , H03M1/167 , H03M1/362
摘要： An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
摘要翻译：偏移校正电路检查管线模数转换器（ADC）的级的残留信号，以确定是否需要调整可能导致偏移误差的参数。在一个实施例中，调整参数直到残差信号的最大范围等于预期范围。在所描述的示例中，经调整的参数包括定时偏移误差（当ADC的分量对不同时间的输入信号进行采样时）和电压偏移误差（在产生子码的阶段中的子ADC的阈值电压更改为下一个值）。

6. 发明授权

US06906658B2 Reducing droop in a reference signal provided to ADCs 有权
标题翻译：减少提供给ADC的参考信号中的下垂
公开(公告)号：US06906658B2
公开(公告)日：2005-06-14
申请号：US10708853
申请日：2004-03-29
申请人： Visvesvaraya A. Pentakota , Gautam Salil Nandi
发明人： Visvesvaraya A. Pentakota , Gautam Salil Nandi
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/0607 , H03M1/12
摘要： An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.
摘要翻译：本发明的一个方面减小提供给ADC的参考信号中的下垂。在参考信号的路径中提供具有适当电阻值的补偿电阻，以使下垂最小化。

7. 发明授权

US08581634B2 Source follower input buffer 有权
标题翻译：源跟踪器输入缓冲器
公开(公告)号：US08581634B2
公开(公告)日：2013-11-12
申请号：US12763945
申请日：2010-04-20
申请人： Nitin Agarwal , Visvesvaraya A. Pentakota
发明人： Nitin Agarwal , Visvesvaraya A. Pentakota
IPC分类号： G11C27/02
CPC分类号： H03K19/018528 , G11C27/024
摘要： Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.
摘要翻译：传统上，模数转换器（ADC）的输入源跟随缓冲器缺乏足够高的线性度。这是由于源极跟随缓冲器必须通过向容性负载提供信号电流来驱动外部电容性负载。这里提供了缓冲器，其包括源极跟随器缓冲器和其它偏置电路（其提供信号电流）。因此，输入电路（即，输入缓冲器）的整体线性度得到改善。

8. 发明申请

US20110102216A1 APPARATUS FOR CORRECTING SETTING ERROR IN AN MDAC AMPLIFIER 有权
标题翻译：用于校正MDAC放大器中的设置错误的装置
公开(公告)号：US20110102216A1
公开(公告)日：2011-05-05
申请号：US12645220
申请日：2009-12-22
申请人： Ganesh Kiran , Visvesvaraya A. Pentakota
发明人： Ganesh Kiran , Visvesvaraya A. Pentakota
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/167 , H03M1/66
摘要： Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capacitor network that compensates for this settling error. Thus, a more accurate pipelined ADC can now be produced.
摘要翻译：通常在流水线模数转换器（ADC）中采用的乘法数字模拟转换器（MDAC）可能会产生与MDAC放大器相关的稳定误差。这里提供了一个电路，其中包括额外的放大器和补偿该稳定误差的电容器网络。因此，现在可以生产更精确的流水线ADC。

9. 发明授权

US07898446B2 Correction of sampling mismatch in time-interleaved analog-to-digital converters 有权
标题翻译：时间交错模数转换器中采样失配的校正
公开(公告)号：US07898446B2
公开(公告)日：2011-03-01
申请号：US12502569
申请日：2009-07-14
申请人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
发明人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
IPC分类号： H03M1/06
CPC分类号： H03M1/0624 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
摘要翻译：提供了时间交织的模数转换器（ADC）。 ADC通常包括第一ADC，第二ADC，校正电路，分频器和时钟电路。第一ADC接收模拟输入信号并产生第一输出和微分输出。第二个ADC接收模拟输入信号并产生第二个输出。校正电路接收第一输出，第二输出和微分输出，并产生第一误差信号和第二误差信号。分频器接收第一误差信号和第二误差信号，并通过将第二误差信号除以第一误差信号产生定时误差，并且时钟电路接收时钟信号和定时误差，并产生多个校正时钟信号，其中第一和第二ADC中的每一个接收至少一个时钟信号。

10. 发明申请

US20100309033A1 CORRECTION OF SAMPLING MISMATCH IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：在时间间隔模拟数字转换器中采样误差校正的校正
公开(公告)号：US20100309033A1
公开(公告)日：2010-12-09
申请号：US12502569
申请日：2009-07-14
申请人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
发明人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
IPC分类号： H03M1/06
CPC分类号： H03M1/0624 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
摘要翻译：提供了时间交织的模数转换器（ADC）。 ADC通常包括第一ADC，第二ADC，校正电路，分频器和时钟电路。第一ADC接收模拟输入信号并产生第一输出和微分输出。第二个ADC接收模拟输入信号并产生第二个输出。校正电路接收第一输出，第二输出和微分输出，并产生第一误差信号和第二误差信号。分频器接收第一误差信号和第二误差信号，并通过将第二误差信号除以第一误差信号产生定时误差，并且时钟电路接收时钟信号和定时误差，并产生多个校正时钟信号，其中第一和第二ADC中的每一个接收至少一个时钟信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式