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1. 发明授权

US07310058B2 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) 有权
标题翻译：减少将模拟输入采样转换为模拟数字转换器（ADC）中数字码的时间，
公开(公告)号：US07310058B2
公开(公告)日：2007-12-18
申请号：US11160859
申请日：2005-07-13
申请人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvaraya A. Pentakota , Sandeep Oswal
发明人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvaraya A. Pentakota , Sandeep Oswal
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

2. 发明授权

US07576668B2 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) 有权
标题翻译：减少将模拟输入采样转换为模拟数字转换器（ADC）中数字码的时间，
公开(公告)号：US07576668B2
公开(公告)日：2009-08-18
申请号：US11934611
申请日：2007-11-02
申请人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvararaya A. Pentakota , Sandeep Oswal
发明人： Anand Hariraj Udupa , Vikas Kumar Sinha , Nitin Agarwal , Visvesvararaya A. Pentakota , Sandeep Oswal
IPC分类号： H03M1/00
CPC分类号： H03M1/168
摘要： A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
摘要翻译：流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC，减法器和放大）。由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

3. 发明授权

US07088149B2 Enhancing SNR and throughput performance of integrated circuits 有权
标题翻译：提高集成电路的SNR和吞吐量性能
公开(公告)号：US07088149B2
公开(公告)日：2006-08-08
申请号：US10724517
申请日：2003-11-29
申请人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota , Shakti Shankar Rath , Gautam Salil Nandi , Vineet Mishra , Ravishankar S. Ayyagari , Nitin Agarwal
发明人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota , Shakti Shankar Rath , Gautam Salil Nandi , Vineet Mishra , Ravishankar S. Ayyagari , Nitin Agarwal
IPC分类号： G11C27/02
CPC分类号： H03F1/26 , H03F3/45188 , H03F3/45475 , H03F3/4565 , H03F3/45937 , H03F3/72
摘要： Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.
摘要翻译：低压晶体管用于高压环境。低电压晶体管可用于处理信号的路径以增加吞吐量性能。通过使用与高压环境相关联的高压电源，可以获得更高的信噪比。实施各种技术以确保低电压晶体管不被长时间暴露于高电压而损坏。

4. 发明授权

US06977547B2 Minimizing changes in the amplification factor of an amplification circuit during operation 有权
标题翻译：最大限度地减少放大电路在放大电路中的变化
公开(公告)号：US06977547B2
公开(公告)日：2005-12-20
申请号：US10722409
申请日：2003-11-28
申请人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota
发明人： Anand Hariraj Udupa , Visvesvaraya A. Pentakota
IPC分类号： H03F3/45
CPC分类号： H03F3/45977
摘要： A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification factor of an amplification circuit during operation.
摘要翻译：在放大器的输出端提供电阻器（或具有不改变的阻抗的部件），这使得放大电路在操作期间的放大系数的变化最小化。

5. 发明授权

US07786909B2 Analog to digital converter with improved input overload recovery 有权
标题翻译：具有改进的输入过载恢复模数转换器
公开(公告)号：US07786909B2
公开(公告)日：2010-08-31
申请号：US12337658
申请日：2008-12-18
申请人： Anand Hariraj Udupa , Neeraj Shrivastava , Nitin Agarwal
发明人： Anand Hariraj Udupa , Neeraj Shrivastava , Nitin Agarwal
IPC分类号： H03M1/06
CPC分类号： H03M1/129 , H03M1/069 , H03M1/164
摘要： With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.
摘要翻译：使用高速模数转换器（ADC）时，当输入超过ADC的输入范围时，ADC内部的器件可能会进入饱和区，从而导致错误。这里，将ADC的输入信号的样本与ADC的上限和下限满量程电平进行比较。如果检测到输入过载，则在输入过载的持续时间内，ADC输入级放大器的输入被强制为零，从而防止输入过饱和。输入过载条件直接发送到ADC的输出数字模块，根据输入过载信号是否超过上限或下限，提供与上限或下限满量程电平相当的输出数字代码。因此可以将ADC的输入过载恢复时间最小化。

6. 发明申请

US20090184853A1 ANALOG TO DIGITAL CONVERTER WITH IMPROVED INPUT OVERLOAD RECOVERY 有权
标题翻译：模拟到具有改进的输入过载恢复的数字转换器
公开(公告)号：US20090184853A1
公开(公告)日：2009-07-23
申请号：US12337658
申请日：2008-12-18
申请人： Anand Hariraj Udupa , Neeraj Shrivastava , Nitin Agarwal
发明人： Anand Hariraj Udupa , Neeraj Shrivastava , Nitin Agarwal
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/129 , H03M1/069 , H03M1/164
摘要： An aspect of the present invention avoids an amplifier of an analog to digital converter (ADC) from entering a saturation region. In an embodiment, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.
摘要翻译：本发明的一个方面避免了模数转换器（ADC）的放大器进入饱和区域。在一个实施例中，将ADC的输入信号的样本与ADC的上限和下限满量程电平进行比较。如果检测到输入过载，则在输入过载的持续时间内，ADC输入级放大器的输入被强制为零，从而防止输入过饱和。输入过载条件直接发送到ADC的输出数字模块，该输出数字模块根据输入过载信号是否超过上限或下限，提供相当于上限或下限满量程级别的输出数字代码。因此可以将ADC的输入过载恢复时间最小化。

7. 发明申请

US20090295363A1 Voltage Reference With Improved Linearity Addressing Variable Impedance Characteristics At Output Node 有权
标题翻译：在输出节点处改进线性度寻址可变阻抗特性的电压基准
公开(公告)号：US20090295363A1
公开(公告)日：2009-12-03
申请号：US12128640
申请日：2008-05-29
申请人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
发明人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
IPC分类号： H03H5/00
CPC分类号： H03H7/38 , H03F3/45475 , H03F2203/45136 , H03F2203/45528 , H03F2203/45534
摘要： A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.
摘要翻译：在输出节点处包含可编程电阻部分的电压基准，其中提供输出参考电压。确定提供电压基准的输出电阻和电压基准的输出电容器的串联电阻的最佳匹配的可编程部分的期望幅度并进行硬编程。结果，电压基准的输出电压具有改善的线性度。在一个实施例中，通过为驱动ADC的电压基准向模数转换器（ADC）提供输入来执行可编程部分的幅度的确定。然后硬编程对应于三次谐波的电阻设定小于期望的阈值。在替代实施例中，可编程部分在操作期间被动态地设置为特定电阻。

8. 发明授权

US06694063B2 Offset correction of the output of a charge coupled device 有权
标题翻译：电荷耦合器件输出的偏移校正
公开(公告)号：US06694063B2
公开(公告)日：2004-02-17
申请号：US09747325
申请日：2000-12-21
申请人： Suhas R. Kulhalli , Supriyo Palit , Sindhuja Sridharan , Shakti Shankar Rath , Anand Hariraj Udupa
发明人： Suhas R. Kulhalli , Supriyo Palit , Sindhuja Sridharan , Shakti Shankar Rath , Anand Hariraj Udupa
IPC分类号： G06K940
CPC分类号： H04N5/2176
摘要： An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for greater correction when error is large, and little correction when the error is small. The exponential curve may be viewed as a sequence of connected linear segments, and the correction to the offset may be determined by the slope of the segment to which the error maps. As the slopes at large errors are steep, the slope is correspondingly high, and the offset converges towards the correct value quickly. Power consumption is optimized by implementing the offset generation circuit using capacitor charge sharing principles.
摘要翻译：偏移用于校正电荷耦合器件（CCD）的输出。通过指数曲线确定偏移量的校正，当指数误差较大时，能够进行更大的校正，而当误差较小时，可以很少校正。指数曲线可以被视为连接的线性段的序列，并且对偏移的校正可以由误差映射到的段的斜率来确定。由于大误差斜率较大，斜率相应较高，偏移量正好快速收敛于正确值。通过使用电容器电荷共享原理实现偏移生成电路来优化功耗。

9. 发明授权

US07898331B2 Increasing the common mode range of a circuit 有权
标题翻译：增加电路的共模范围
公开(公告)号：US07898331B2
公开(公告)日：2011-03-01
申请号：US11164503
申请日：2005-11-28
申请人： Anand Hariraj Udupa , Jagannathan Venkataraman
发明人： Anand Hariraj Udupa , Jagannathan Venkataraman
IPC分类号： H03F3/45
CPC分类号： H03F3/45 , H03F3/45479
摘要： Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.
摘要翻译：增加接收差分信号作为输入的电路的输入共模范围。这种增加可以通过以连续电平或2个或更多个离散电平校正输入信号而不改变由输入信号表示的强度来实现。在一个实施例中，测量输入信号的共模分量，并且产生与所测量的共模分量与参考电压之间的差成比例的校正电压。校正电压耦合到差分电路的输入端，以校正在差分电路的输入端处与共模电压的期望电平的任何偏差。这些方法被应用于在ADC的采样和保持部分中使用的开关电容差分放大器。

10. 发明授权

US08248055B2 Voltage reference with improved linearity addressing variable impedance characteristics at output node 有权
标题翻译：电压基准，改善线性度，寻址输出节点的可变阻抗特性
公开(公告)号：US08248055B2
公开(公告)日：2012-08-21
申请号：US12128640
申请日：2008-05-29
申请人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
发明人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
IPC分类号： G05F3/16 , G05F1/648
CPC分类号： H03H7/38 , H03F3/45475 , H03F2203/45136 , H03F2203/45528 , H03F2203/45534
摘要： A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.
摘要翻译：在输出节点处包含可编程电阻部分的电压基准，其中提供输出参考电压。确定提供电压基准的输出电阻和电压基准的输出电容器的串联电阻的最佳匹配的可编程部分的期望幅度并进行硬编程。结果，电压基准的输出电压具有改善的线性度。在一个实施例中，通过为驱动ADC的电压基准向模数转换器（ADC）提供输入来执行可编程部分的幅度的确定。然后硬编程对应于三次谐波的电阻设定小于期望的阈值。在替代实施例中，可编程部分在操作期间被动态地设置为特定电阻。

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