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1. 发明授权

US4933733A Slot collector transistor 失效
标题翻译：槽集电极晶体管
公开(公告)号：US4933733A
公开(公告)日：1990-06-12
申请号：US929543
申请日：1986-11-12
申请人： Ali Iranmanesh , Christopher O. Schmidt
发明人： Ali Iranmanesh , Christopher O. Schmidt
IPC分类号： H01L29/06 , H01L29/08 , H01L29/732
CPC分类号： H01L29/0649 , H01L29/0821 , H01L29/732 , H01L29/7325
摘要： An improved semiconductor device is presented, the improvement comprising a slot collector contact region (38). The slot collector contact region (38) is formed in a semiconductor substrate (39) adjacent to base and emitter regions (40,44) of the bipolar semiconductor device. The slot collector contact region (38) is comprised of a slot filled with a filler material. In a preferred embodiment of the invention, the slot collector contact region (38) is separated from the base and emitter regions (40,44) by an insulating layer (52).
摘要翻译：提出了一种改进的半导体器件，其改进包括狭缝集电器接触区域（38）。狭缝集电极接触区域（38）形成在与双极半导体器件的基极和发射极区域（40,44）相邻的半导体衬底（39）中。狭槽收集器接触区域（38）由填充有填充材料的槽组成。在本发明的优选实施例中，槽集电极接触区域（38）通过绝缘层（52）与基极和发射极区域（40,44）分离。

2. 发明授权

US4641416A Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter 失效
标题翻译：制造具有自对准氧化的集成电路结构以从发射极隔离外部基极的方法
公开(公告)号：US4641416A
公开(公告)日：1987-02-10
申请号：US707730
申请日：1985-03-04
申请人： Ali Iranmanesh , Christopher O. Schmidt
发明人： Ali Iranmanesh , Christopher O. Schmidt
IPC分类号： H01L21/331 , H01L21/762 , H01L29/06 , H01L21/302 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/76221 , H01L29/0649 , Y10S148/01 , Y10S148/05 , Y10S148/085 , Y10S148/117 , Y10S438/911
摘要： The invention comprises an improved integrated circuit structure wherein an active device is formed in a silicon substrate for forming an intrinsic base region over a buried collector and an emitter is formed on the intrinsic base region to comprise three electrodes of the active device and at least one extrinsic base segment is formed in the substrate adjacent to the intrinsic base region to provide a contact for the intrinsic base; the improvement which comprises: separating the extrinsic base segment from the emitter formed on the intrinsic base to prevent the formation of a parasitic P-N junction between the extrinsic base and the emitter.
摘要翻译：本发明包括改进的集成电路结构，其中有源器件形成在硅衬底中，用于在掩埋集电极上形成本征基极区域，并且发射极形成在本征基极区域上，以包括有源器件的三个电极和至少一个在与本征基区相邻的衬底中形成非本征基区以提供本征碱的接触; 其改进包括：从本征基底上形成的发射极分离外部基极区段，以防止在外部基极和发射极之间形成寄生的P-N结。

3. 发明授权

US06291327B1 Optimization of S/D annealing to minimize S/D shorts in memory array 失效
标题翻译：优化S / D退火以最小化存储器阵列中的S / D短路
公开(公告)号：US06291327B1
公开(公告)日：2001-09-18
申请号：US09192094
申请日：1998-11-13
申请人： Xiao-Yu Li , Sunil D. Mehta , Christopher O. Schmidt , Robert H. Tu
发明人： Xiao-Yu Li , Sunil D. Mehta , Christopher O. Schmidt , Robert H. Tu
IPC分类号： H01L21336
CPC分类号： H01L21/76237 , H01L21/823418 , H01L21/823462 , H01L27/1052
摘要： A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.
摘要翻译：提供了一种用于消除在标准STI工艺中的高掺杂源极/漏极注入步骤期间产生的源极/漏极短路的方法。这是通过将RTA温度降低至小于1000℃来实现的，以便使增强的掺杂扩散最小化。此外，高掺杂源极/漏极注入步骤的能级增加，以补偿栅电极中的多晶硅耗尽。

4. 发明授权

US6157568A Avalanche programmed floating gate memory cell structure with program element in first polysilicon layer 有权
标题翻译：雪崩编程浮栅存储单元结构与第一多晶硅层中的程序元件
公开(公告)号：US6157568A
公开(公告)日：2000-12-05
申请号：US220469
申请日：1998-12-23
申请人： Christopher O. Schmidt
发明人： Christopher O. Schmidt
IPC分类号： G11C16/04 , H01L21/28 , H01L27/115 , H01L27/12 , H01L29/51 , H01L29/788 , G11C11/34
CPC分类号： H01L29/7886 , G11C16/0441 , H01L27/115 , H01L27/1203 , H01L29/511 , H01L21/28194
摘要： A non-volatile memory cell structure which includes a floating gate, at least one injection element and a sense transistor. The injection element is at least partially formed in a first polysilicon layer. The floating gate is provided in a second polysilicon layer and capacitively coupled to the reverse breakdown element. The sense transistor is at least partially formed in a region of a semiconductor substrate, and connected to the floating gate. The structure may further comprise a control gate capacitively coupled to the floating gate and may be formed in said first polysilicon layer.
摘要翻译：一种非易失性存储单元结构，其包括浮置栅极，至少一个注入元件和感测晶体管。注入元件至少部分地形成在第一多晶硅层中。浮置栅极设置在第二多晶硅层中，并电容耦合到反向击穿元件。感测晶体管至少部分地形成在半导体衬底的区域中，并连接到浮置栅极。该结构还可以包括电容耦合到浮置栅极并且可以形成在所述第一多晶硅层中的控制栅极。

5. 发明授权

US4622738A Method of making integrated bipolar semiconductor device by first forming junction isolation regions and recessed oxide isolation regions without birds beak 失效
标题翻译：通过首先形成结隔离区域和没有鸟喙的凹陷氧化物隔离区域来制造集成双极半导体器件的方法
公开(公告)号：US4622738A
公开(公告)日：1986-11-18
申请号：US720824
申请日：1985-04-08
申请人： Peter S. Gwozdz , Christopher O. Schmidt , William L. Price
发明人： Peter S. Gwozdz , Christopher O. Schmidt , William L. Price
IPC分类号： H01L21/331 , H01L21/761 , H01L21/762 , H01L21/265 , H01L21/225
CPC分类号： H01L29/66272 , H01L21/761 , H01L21/76221 , Y10S148/01 , Y10S438/981
摘要： A method is presented for fabricating a bipolar semiconductor device utilizing a combination of junction isolation, oxide isolation, stepper lithography and plasma etching to produce an integrated circuit device having reduced device sizes and increased performance. The method includes the steps of removing portions of a masking layer to expose surface areas of an epitaxial layer, where first type isolation regions are then formed; then forming second type isolation regions in the epitaxial layer, and forming base, emitter and collector contact regions, also in the epitaxial layer; and forming conductive lines on the base, emitter and collector contact regions.
摘要翻译：提出了一种利用结隔离，氧化物隔离，步进光刻和等离子体蚀刻的组合来制造双极半导体器件以产生具有减小的器件尺寸和增加的性能的集成电路器件的方法。该方法包括以下步骤：去除掩模层的部分以暴露外延层的表面区域，然后形成第一类型的隔离区域; 然后在所述外延层中形成第二类型隔离区，并且还在所述外延层中形成基极，发射极和集电极接触区; 并在基极，发射极和集电极接触区域上形成导线。

6. 发明授权

US06424003B1 EEPROM cell with self-aligned tunneling window 有权
公开(公告)号：US06424003B1
公开(公告)日：2002-07-23
申请号：US09169492
申请日：1998-10-09
申请人： Xiao Yu Li , Sunil D. Mehta , Christopher O. Schmidt
发明人： Xiao Yu Li , Sunil D. Mehta , Christopher O. Schmidt
IPC分类号： H07L29788
摘要： An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.

7. 发明授权

US06232631B1 Floating gate memory cell structure with programming mechanism outside the read path 失效
标题翻译：浮动门存储单元结构，具有读取路径外的编程机制
公开(公告)号：US06232631B1
公开(公告)日：2001-05-15
申请号：US09217648
申请日：1998-12-21
申请人： Christopher O. Schmidt , Sunil D. Mehta
发明人： Christopher O. Schmidt , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： G11C16/0441 , H01L27/115
摘要： A non-volatile memory cell structure includes a floating gate, a reverse breakdown hot carrier injection element and a sense transistor. The reverse breakdown hot carrier injection element is at least partially formed in a first region of a semiconductor substrate under at least a portion of the floating gate. The sense transistor is at least partially formed in a second region of a semiconductor substrate, isolated from the first region, and under at least a portion of the floating gate. A read transistor may be connected to the sense transistor. In one embodiment, the read transistor is at least partially formed in the second region of a semiconductor substrate, and connected to the sense transistor.
摘要翻译：非易失性存储单元结构包括浮置栅极，反向击穿热载流子注入元件和感测晶体管。反向击穿热载流子注入元件至少部分地形成在半导体衬底的至少一部分浮动栅极的第一区域内。感测晶体管至少部分地形成在半导体衬底的与第一区域隔离的第二区域中，并且至少部分地形成在浮置栅极的至少一部分下方。读取晶体管可以连接到感测晶体管。在一个实施例中，读取晶体管至少部分地形成在半导体衬底的第二区域中，并连接到感测晶体管。

8. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

9. 发明授权

US4795721A Walled slot devices and method of making same 失效
标题翻译：围墙设备及其制作方法
公开(公告)号：US4795721A
公开(公告)日：1989-01-03
申请号：US897685
申请日：1986-08-18
申请人： Robert W. Bower , Christopher O. Schmidt
发明人： Robert W. Bower , Christopher O. Schmidt
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/763 , H01L27/04 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/267 , H01L29/735 , H01L29/06
CPC分类号： H01L21/763 , H01L21/743 , H01L29/04 , H01L29/0804 , H01L29/1004 , H01L29/735
摘要： An improved integrated circuit structure is disclosed which comprises a substrate having one or more active device slots with active elements of an active device formed therein and an isolation slot surrounding the one or more active device slots with an inner wall contiguous with the outer wall of the one or more active device slots. The active elements in the one or more active device slots are thereby in direct contact with isolation material in the isolation slot to thereby inhibit end effects.
摘要翻译：公开了一种改进的集成电路结构，其包括具有一个或多个有源器件槽的衬底，所述有源器件槽具有形成在其中的有源器件的有源元件，以及围绕所述一个或多个有源器件槽的隔离槽，所述隔离槽具有与所述一个或多个活动的设备插槽。因此，一个或多个有源器件槽中的有源元件与隔离槽中的隔离材料直接接触，从而抑制最终效应。

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