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1. 发明授权

US4622738A Method of making integrated bipolar semiconductor device by first forming junction isolation regions and recessed oxide isolation regions without birds beak 失效
标题翻译：通过首先形成结隔离区域和没有鸟喙的凹陷氧化物隔离区域来制造集成双极半导体器件的方法
公开(公告)号：US4622738A
公开(公告)日：1986-11-18
申请号：US720824
申请日：1985-04-08
申请人： Peter S. Gwozdz , Christopher O. Schmidt , William L. Price
发明人： Peter S. Gwozdz , Christopher O. Schmidt , William L. Price
IPC分类号： H01L21/331 , H01L21/761 , H01L21/762 , H01L21/265 , H01L21/225
CPC分类号： H01L29/66272 , H01L21/761 , H01L21/76221 , Y10S148/01 , Y10S438/981
摘要： A method is presented for fabricating a bipolar semiconductor device utilizing a combination of junction isolation, oxide isolation, stepper lithography and plasma etching to produce an integrated circuit device having reduced device sizes and increased performance. The method includes the steps of removing portions of a masking layer to expose surface areas of an epitaxial layer, where first type isolation regions are then formed; then forming second type isolation regions in the epitaxial layer, and forming base, emitter and collector contact regions, also in the epitaxial layer; and forming conductive lines on the base, emitter and collector contact regions.
摘要翻译：提出了一种利用结隔离，氧化物隔离，步进光刻和等离子体蚀刻的组合来制造双极半导体器件以产生具有减小的器件尺寸和增加的性能的集成电路器件的方法。该方法包括以下步骤：去除掩模层的部分以暴露外延层的表面区域，然后形成第一类型的隔离区域; 然后在所述外延层中形成第二类型隔离区，并且还在所述外延层中形成基极，发射极和集电极接触区; 并在基极，发射极和集电极接触区域上形成导线。

2. 发明授权

US4639288A Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching 失效
标题翻译：使用各向同性和各向异性蚀刻在集成电路结构中形成沟槽的工艺
公开(公告)号：US4639288A
公开(公告)日：1987-01-27
申请号：US668225
申请日：1984-11-05
申请人： William L. Price , Ronald L. Schlupp , Mammen Thomas
发明人： William L. Price , Ronald L. Schlupp , Mammen Thomas
IPC分类号： H01L21/76 , H01L21/3065 , H01L21/308 , H01L21/762 , H01L21/763 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76232 , H01L21/3065 , H01L21/3081 , H01L21/3085 , H01L21/763
摘要： An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.
摘要翻译：公开了一种用于制造集成电路结构的改进方法，其中沟槽被蚀刻成一个或多个层，以将集成电路结构中的一个器件与其它部分电气分离，首先在二层二氧化硅和氮化硅层硅。该改进包括各向同性地蚀刻硅层以提供底部图案化的二氧化硅和氮化硅层的扩大的浅蚀刻区域。随后进行更深的各向异性蚀刻以形成沟槽将导致具有扩大的上部宽度的沟槽，这继而在随后的氧化和多晶硅沉积步骤期间防止邻近沟槽上部的空隙的形成。从而消除了在随后的平坦化期间可能在多晶硅中产生这种空隙的开口，从而避免了这种空隙的不期望的氧化和由此产生的不期望的应力。

3. 发明授权

US4575814A Programmable interface memory 失效
标题翻译：可编程接口存储器
公开(公告)号：US4575814A
公开(公告)日：1986-03-11
申请号：US382318
申请日：1982-05-26
申请人： Charles W. Brooks, Jr. , William L. Price
发明人： Charles W. Brooks, Jr. , William L. Price
IPC分类号： G06F12/02 , G06F13/00
CPC分类号： G06F12/0207
摘要： A digital signal processing system and more especially a programmable bulk memory included therein comprising a plurality of memory sections independently controlled and simultaneously operative for transferring blocks or vectors of digital data words directly between selected memory sections and external data handling units while maintaining the corresponding variety of data handling throughput rates thereof without the need for input-output buffer type memories coupled therebetween is disclosed. A method of addressing the sections of addressable memory locations for accessing therefrom and storing therein blocks of data words in accordance with predetermined sequences is also disclosed.
摘要翻译：一种数字信号处理系统，更具体地包括其中包括的可编程大容量存储器，其包括多个存储器部分，其独立地被控制并同时用于直接在选择的存储器部分和外部数据处理单元之间传送数字数据字的块或矢量，同时保持相应的各种公开了其数据处理吞吐率，而不需要在其间连接的输入 - 输出缓冲器型存储器。还公开了一种寻址可寻址存储器位置的部分以便从其访问并存储其中根据预定序列的数据字块的方法。

4. 发明授权

US4135295A Process of making platinum silicide fuse links for integrated circuit devices 失效
标题翻译：为集成电路器件制造铂硅化物熔断体的工艺
公开(公告)号：US4135295A
公开(公告)日：1979-01-23
申请号：US807806
申请日：1977-06-20
申请人： William L. Price
发明人： William L. Price
IPC分类号： H01L23/525 , H01L23/62 , H01H69/02
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , Y10S148/02 , Y10S148/055 , Y10T29/49107
摘要： Selected circuit elements and interconnections of an integrated circuit device are connected by platinum silicide fuse links which open when electrical power exceeds a threshold amount. The fuse is constructed by defining the fuse geometry in a polycrystalline silicon layer over a wafer substrate, depositing a layer of platinum thereover and then sintering the platinum into the polysilicon.
摘要翻译：集成电路器件的所选择的电路元件和互连通过铂硅化物熔断体连接，当电功率超过阈值时，它们断开。熔丝通过在晶片衬底上的多晶硅层中限定熔丝几何结构，在其上沉积铂层，然后将铂烧结到多晶硅中而构成。

5. 发明授权

US4447873A Input-output buffers for a digital signal processing system 失效
标题翻译：用于数字信号处理系统的输入输出缓冲器
公开(公告)号：US4447873A
公开(公告)日：1984-05-08
申请号：US146934
申请日：1980-05-05
申请人： William L. Price , John C. Murtha , James A. Ross, Jr. , Clyde E. Adam , Kenneth R. Lucas
发明人： William L. Price , John C. Murtha , James A. Ross, Jr. , Clyde E. Adam , Kenneth R. Lucas
IPC分类号： G06F9/345 , G06F13/12 , G06F3/04 , G06F13/00
CPC分类号： G06F13/122 , G06F9/345
摘要： Input-output buffers interface a data terminal, such as a digital signal processor adapted to perform complex arithmetic functions on vectors of data words, with a storage controller. The input buffer interfaces the storage controller with the data terminal and generates control signals indicating when it is in condition to receive a vector of data words from the storage controller, whereon the storage controller transfers a vector of data to the input buffer; and, further, generates signals indicating when it contains a complete vector of data at which time the input buffer will transfer the vector of data contained therein to the data terminal. Each output buffer interfaces the data terminal with the storage controller and generates control signals indicating when it is in condition to receive a vector of data whereon a vector of data will be transferred from the data terminal to the output buffer; and, further, generates signals indicating when it contains a complete vector of data at which time the output buffer will transfer the vector contained therein to the storage controller.
摘要翻译：输入输出缓冲器将数据终端（诸如适于对数据字的向量执行复杂算术功能的数字信号处理器）与存储控制器进行接口。所述输入缓冲器将所述存储控制器与所述数据终端接口，并产生指示何时从存储控制器接收数据字的向量的控制信号，所述存储控制器将所述数据向量传送到所述输入缓冲器; 并且还产生指示何时它包含完整的数据向量的信号，此时输入缓冲器将其中包含的数据的向量传送到数据终端。每个输出缓冲器将数据终端与存储控制器接口，并产生指示何时接收数据向量的条件的控制信号，其中数据向量将从数据终端传送到输出缓冲器; 并且还产生指示何时它包含完整的数据向量的信号，此时输出缓冲器将其中所包含的向量传送到存储控制器。

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