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1. 发明申请

US20130123159A1 AQUEOUS CERIUM-CONTAINING SOLUTION HAVING AN EXTENDED BATH LIFETIME FOR REMOVING MASK MATERIAL 失效
标题翻译：含有延长护罩寿命的含有水溶液的解决方案可用于去除面膜材料
公开(公告)号：US20130123159A1
公开(公告)日：2013-05-16
申请号：US13295677
申请日：2011-11-14
申请人： Ali Afzali-Ardakani , John A. Fitzsimmons , Nicholas C.M. Fuller , Mahmoud Khojasteh , Jennifer V. Muncy , George G. Totir , Karl E. Boggs , Emanuel I. Cooper , Michael W. Owens , James L. Simpson
发明人： Ali Afzali-Ardakani , John A. Fitzsimmons , Nicholas C.M. Fuller , Mahmoud Khojasteh , Jennifer V. Muncy , George G. Totir , Karl E. Boggs , Emanuel I. Cooper , Michael W. Owens , James L. Simpson
IPC分类号： G03F7/42
CPC分类号： H01L21/31133 , C09K13/04 , G03F7/423 , G03F7/425 , G03F7/426
摘要： An aqueous solution of a cerium (IV) complex or salt having an extended lifetime is provided. In one embodiment, the extended lifetime is achieved by adding at least one booster additive to an aqueous solution of the cerium (IV) complex or salt. In another embodiment, the extended lifetime is achieved by providing an aqueous solution of a cerium (IV) complex or salt and a cerium (III) complex or salt. The cerium (III) complex or salt can be added or it can be generated in-situ by introducing a reducing agent into the aqueous solution of the cerium (IV) complex or salt. The aqueous solution can be used to remove a mask material, especially an ion implanted and patterned photoresist, from a surface of a semiconductor substrate.
摘要翻译：提供具有延长寿命的铈（IV）络合物或盐的水溶液。在一个实施方案中，通过向铈（IV）络合物或盐的水溶液中加入至少一种助剂添加剂来实现延长的寿命。在另一个实施方案中，通过提供铈（IV）络合物或盐和铈（III）络合物或盐的水溶液来实现延长的寿命。可以加入铈（III）络合物或盐，或者可以通过将还原剂引入铈（IV）络合物或盐的水溶液中而原位产生。水溶液可用于从半导体衬底的表面去除掩模材料，特别是离子注入和图案化的光致抗蚀剂。

2. 发明申请

US20130143397A1 USE OF AN ORGANIC PLANARIZING MASK FOR CUTTING A PLURALITY OF GATE LINES 失效
标题翻译：使用有机平面化掩模切割大量的浇口线
公开(公告)号：US20130143397A1
公开(公告)日：2013-06-06
申请号：US13612981
申请日：2012-09-13
申请人： Nicholas C.M. Fuller , Pratik P. Joshi , Mahmoud Khojasteh , Rajiv M. Ranade , George G. Totir
发明人： Nicholas C.M. Fuller , Pratik P. Joshi , Mahmoud Khojasteh , Rajiv M. Ranade , George G. Totir
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/31133 , H01L21/823437 , H01L21/823828
摘要： An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
摘要翻译：在其上包括多条栅极线的半导体衬底上形成有机平面化层（OPL）。每个栅极线包括至少一个高k栅极电介质和金属栅极。然后将其中形成有至少一种图案的图案化的光致抗蚀剂定位在OPL的顶部。光致抗蚀剂中的至少一个图案垂直于每个栅极线。然后通过蚀刻将图案转移到OPL和每个下面的栅极线的部分，以提供多个栅极堆叠，每个栅极堆叠包括至少一个高k栅极电介质部分和金属栅极部分。然后使用一系列步骤除去图案化的光致抗蚀剂和剩余的OPL层，所述步骤包括首先与第一酸接触，第二次与含铈水溶液接触，并且与第二次酸接触。

3. 发明申请

US20120193715A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20120193715A1
公开(公告)日：2012-08-02
申请号：US13442008
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接的氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

4. 发明申请

US20080305437A1 MULTI-LAYER MASK METHOD FOR PATTERNED STRUCTURE ETHCING 审中-公开
标题翻译：多层结构的多层掩模方法
公开(公告)号：US20080305437A1
公开(公告)日：2008-12-11
申请号：US11760992
申请日：2007-06-11
申请人： Nicholas C.M. Fuller , Michael A. Guillorn , Francois Pagette , Balasubramanian Pranatharthiharan , Ying Zhang
发明人： Nicholas C.M. Fuller , Michael A. Guillorn , Francois Pagette , Balasubramanian Pranatharthiharan , Ying Zhang
IPC分类号： G03C5/00
CPC分类号： H01L21/28123 , H01L21/31116 , H01L21/32136 , H01L29/7833
摘要： A method for forming a patterned structure within a microelectronic structure uses a non-directly imageable organic material layer located over a substrate and a directly imageable inorganic material layer located upon the non-directly imageable organic material layer. The directly imageable inorganic material layer is directly imaged to form a patterned inorganic material layer. The patterned inorganic material layer is used as a first etch mask within a first etch method that etches the non-directly imageable organic material layer to form a patterned organic material layer. At least the patterned organic material layer is used as a second etch mask within a second etch method that etches the substrate to form a patterned structure within the substrate.
摘要翻译：用于在微电子结构内形成图案化结构的方法使用位于基底上的非直接成像的有机材料层和位于不可直接成像的有机材料层上的可直接成像的无机材料层。可直接成像无机材料层直接成像以形成图案化的无机材料层。图案化的无机材料层在第一蚀刻方法中用作第一蚀刻掩模，其蚀刻非直接成像的有机材料层以形成图案化的有机材料层。至少图案化的有机材料层在第二蚀刻方法中用作第二蚀刻掩模，其蚀刻衬底以在衬底内形成图案化结构。

5. 发明申请

US20120193680A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
公开(公告)号：US20120193680A1
公开(公告)日：2012-08-02
申请号：US13442011
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/78 , H01L21/306 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

6. 发明申请

US20080311744A1 MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS 有权
标题翻译：用于SiCOH电介质的无损伤双面加工的多层HARDMASK方案
公开(公告)号：US20080311744A1
公开(公告)日：2008-12-18
申请号：US12198602
申请日：2008-08-26
申请人： Nicholas C.M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C.M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： H01L21/768
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.
摘要翻译：具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

7. 发明申请

US20130087860A1 BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS 有权
标题翻译：无边界自对准的金属接触方式使用可印制的电介质材料
公开(公告)号：US20130087860A1
公开(公告)日：2013-04-11
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译：无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。该方法还包括在封闭区域内沉积金属层。这样形成的金属触点与封闭区域自对准。

8. 发明申请

US20090202952A1 SUBLITHOGRAPHIC PATTERNING METHOD INCORPORATING A SELF-ALIGNED SINGLE MASK PROCESS 有权
标题翻译：自动对准单掩模过程的分层方案
公开(公告)号：US20090202952A1
公开(公告)日：2009-08-13
申请号：US12028861
申请日：2008-02-11
申请人： David W. Abraham , Steven E. Steen , Nicholas C.M. Fuller , Francois Pagette
发明人： David W. Abraham , Steven E. Steen , Nicholas C.M. Fuller , Francois Pagette
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , H01L21/32139
摘要： A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.
摘要翻译：实现半导体器件的次光刻图案化的方法包括用单个光刻步骤形成第一组图案化特征，初始的图案化特征集合以其间的线宽和间距为特征; 在所述第一组图案化特征上形成第一组侧壁间隔物，然后移除所述第一组图案特征，以便基于所述第一组侧壁间隔物的几何形状限定第二组图案特征; 以及执行在随后的图案化特征集合上形成随后的一组侧壁间隔物的一个或多个附加迭代，随后移除随后的一组图案化特征，其中给定的一组图案化特征基于相关联的一组侧壁的几何形状间隔物在其之前形成，并且其中后续的一组图案化特征的最后的特征在于亚光刻尺寸。

9. 发明申请

US20110062494A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 有权
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20110062494A1
公开(公告)日：2011-03-17
申请号：US12561704
申请日：2009-09-17
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/78 , H01L21/20 , H01L29/06 , H01L21/302
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

10. 发明申请

US20110006367A1 GATE PATTERNING OF NANO-CHANNEL DEVICES 失效
标题翻译： NANO通道设备的门控方案
公开(公告)号：US20110006367A1
公开(公告)日：2011-01-13
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L27/12
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

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