专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110006367A1 GATE PATTERNING OF NANO-CHANNEL DEVICES 失效
标题翻译： NANO通道设备的门控方案
公开(公告)号：US20110006367A1
公开(公告)日：2011-01-13
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L27/12
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

2. 发明授权

US08445948B2 Gate patterning of nano-channel devices 失效
标题翻译：纳米通道器件的栅极图案化
公开(公告)号：US08445948B2
公开(公告)日：2013-05-21
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine-and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

3. 发明授权

US07816275B1 Gate patterning of nano-channel devices 有权
标题翻译：纳米通道器件的栅极图案化
公开(公告)号：US07816275B1
公开(公告)日：2010-10-19
申请号：US12417954
申请日：2009-04-03
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/00
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

4. 发明申请

US20100252810A1 GATE PATTERNING OF NANO-CHANNEL DEVICES 有权
标题翻译： NANO通道设备的门控方案
公开(公告)号：US20100252810A1
公开(公告)日：2010-10-07
申请号：US12417954
申请日：2009-04-03
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/41 , H01L21/306 , H01L21/302
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

5. 发明授权

US08546269B2 Top-down nanowire thinning processes 失效
标题翻译：自上而下的纳米线稀疏过程
公开(公告)号：US08546269B2
公开(公告)日：2013-10-01
申请号：US12417936
申请日：2009-04-03
申请人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
发明人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
IPC分类号： H01L21/302 , H01L21/461 , H01L29/06
CPC分类号： H01L21/02238 , B82Y10/00 , B82Y30/00 , H01L21/02255 , H01L21/30604 , H01L29/0665 , H01L29/0676 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
摘要翻译：提供了制造基于纳米线的器件的技术。一方面，提供一种制造半导体器件的方法，包括以下步骤。提供了在掩埋氧化物（BOX）层上方具有绝缘体上硅（SOI）层的晶片。将纳米线和焊盘蚀刻到SOI层中以形成阶梯状结构，其中焊盘附着在纳米线的相对端。 BOX层在纳米线下面被切下。纳米线和焊盘与氧化气体接触，以在通过氧化在纳米线上产生硅消耗速率与硅消耗速率之比的条件下，在纳米线和焊盘中氧化硅，焊盘上的氧化从约0.75降至约1.25。在使纳米线和焊盘与氧化气体接触之前，可以统一所有纳米线中的宽度与厚度的纵横比。

6. 发明申请

US20100255680A1 Top-Down Nanowire Thinning Processes 失效
标题翻译：自上而下的纳米线变薄过程
公开(公告)号：US20100255680A1
公开(公告)日：2010-10-07
申请号：US12417936
申请日：2009-04-03
申请人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
发明人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
IPC分类号： H01L21/306
CPC分类号： H01L21/02238 , B82Y10/00 , B82Y30/00 , H01L21/02255 , H01L21/30604 , H01L29/0665 , H01L29/0676 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
摘要翻译：提供了制造基于纳米线的器件的技术。一方面，提供一种制造半导体器件的方法，包括以下步骤。提供了在掩埋氧化物（BOX）层上方具有绝缘体上硅（SOI）层的晶片。将纳米线和焊盘蚀刻到SOI层中以形成阶梯状结构，其中焊盘附着在纳米线的相对端。 BOX层在纳米线下面被切下。纳米线和焊盘与氧化气体接触，以在通过氧化在纳米线上产生硅消耗速率与硅消耗速率之比的条件下，在纳米线和焊盘中氧化硅，焊盘上的氧化从约0.75降至约1.25。在使纳米线和焊盘与氧化气体接触之前，可以统一所有纳米线中的宽度与厚度的纵横比。

7. 发明授权

US08940548B2 Sensor for biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US08940548B2
公开(公告)日：2015-01-27
申请号：US13552727
申请日：2012-07-19
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/552 , G01N33/543 , B82Y10/00 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.
摘要翻译：用于感测电解质中的生物分子的方法包括将包含硅翅片的传感器的栅极电介质表面暴露于电解质，其中所述栅极电介质表面包括电介质材料和被配置为与所述生物分子结合的抗体; 对浸在电解质中的电极施加栅极电压; 并测量在硅片中流动的漏极电流的变化; 以及基于漏极电流的变化确定存在于电解质中的生物分子的量。

8. 发明授权

US08691675B2 Vapor phase deposition processes for doping silicon 失效
标题翻译：掺杂硅的气相沉积工艺
公开(公告)号：US08691675B2
公开(公告)日：2014-04-08
申请号：US12625835
申请日：2009-11-25
申请人： Ali Afzali-Ardakani , Damon B. Farmer , Lidija Sekaric
发明人： Ali Afzali-Ardakani , Damon B. Farmer , Lidija Sekaric
IPC分类号： H01L21/04
CPC分类号： H01L21/2254
摘要： A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.
摘要翻译：用掺杂剂原子掺杂硅层的方法通常包括使掺杂剂前体的蒸气与存在于硅层上的氧化物和/或氢氧化物反应性位点反应以形成掺杂剂前体的自组装单层; 用水蒸汽水解掺杂剂前体的自组装单层以在掺杂剂前体上形成侧基羟基; 用氧化物层封闭自组装单层; 以及在有效地将掺杂剂原子从掺杂剂前体扩散到硅层中的温度下退火硅层。可以以类似的方式形成另外的单层，由此提供受控的掺杂剂前体化合物的逐层气相沉积用于硅的受控掺杂。

9. 发明授权

US08513642B2 Patterned doping of semiconductor substrates using photosensitive monolayers 失效
公开(公告)号：US08513642B2
公开(公告)日：2013-08-20
申请号：US13541857
申请日：2012-07-05
申请人： Ali Afzali-Ardakani , Devendra K. Sadana , Lidija Sekaric
发明人： Ali Afzali-Ardakani , Devendra K. Sadana , Lidija Sekaric
IPC分类号： H01L29/06
CPC分类号： H01L21/228 , H01L21/22 , H01L29/06
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

10. 发明授权

US08368125B2 Multiple orientation nanowires with gate stack stressors 失效
标题翻译：具有栅堆叠应力的多取向纳米线
公开(公告)号：US08368125B2
公开(公告)日：2013-02-05
申请号：US12505580
申请日：2009-07-20
申请人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译：电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加取决于通道长度相对于晶体结构的对准。给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式