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1. 发明申请

US20130087860A1 BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS 有权
标题翻译：无边界自对准的金属接触方式使用可印制的电介质材料
公开(公告)号：US20130087860A1
公开(公告)日：2013-04-11
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译：无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。该方法还包括在封闭区域内沉积金属层。这样形成的金属触点与封闭区域自对准。

2. 发明授权

US09018090B2 Borderless self-aligned metal contact patterning using printable dielectric materials 有权
标题翻译：使用可印刷电介质材料的无边界自对准金属接触图案
公开(公告)号：US09018090B2
公开(公告)日：2015-04-28
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8234
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译：无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。该方法还包括在封闭区域内沉积金属层。这样形成的金属触点与封闭区域自对准。

3. 发明申请

US20110127492A1 Field Effect Transistor Having Nanostructure Channel 审中-公开
标题翻译：具有纳米结构通道的场效应晶体管
公开(公告)号：US20110127492A1
公开(公告)日：2011-06-02
申请号：US12627057
申请日：2009-11-30
申请人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph
发明人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译：场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极，纳米结构。

4. 发明授权

US08288236B2 Field effect transistor having nanostructure channel 有权
标题翻译：具有纳米结构通道的场效应晶体管
公开(公告)号：US08288236B2
公开(公告)日：2012-10-16
申请号：US13345252
申请日：2012-01-06
申请人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph
发明人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph
IPC分类号： H01L21/336
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译：场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极，纳米结构。

5. 发明申请

US20120108024A1 FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL 有权
标题翻译：具有纳米结构通道的场效应晶体管
公开(公告)号：US20120108024A1
公开(公告)日：2012-05-03
申请号：US13345252
申请日：2012-01-06
申请人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph
发明人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译：场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极，纳米结构。

6. 发明授权

US08431486B2 Interconnect structure for improved time dependent dielectric breakdown 有权
标题翻译：互连结构，用于改善时间依赖介质击穿
公开(公告)号：US08431486B2
公开(公告)日：2013-04-30
申请号：US12853537
申请日：2010-08-10
申请人： Cyril Cabral, Jr. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
发明人： Cyril Cabral, Jr. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/31116 , H01L21/32136 , H01L21/32139 , H01L21/76804 , H01L21/76877 , H01L21/76885 , H01L23/5283 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.
摘要翻译：本公开提供了形成到电气设备的互连的方法。在一个实施例中，形成互连的方法包括在衬底上提供器件层，其中所述器件层包括至少一个电器件，在所述至少一个电器件上的入口电介质，以及与所述至少一个电器件电连接的触点所述至少一个电气设备。在器件层上形成互连金属层，并且在互连金属层的一部分上形成含钽蚀刻掩模。蚀刻互连金属层以提供与至少一个电气设备连通的梯形互连。梯形互连具有与器件层接触的第一表面，其具有比与含钽蚀刻掩模接触的梯形互连的第二表面更大的宽度。

7. 发明申请

US20120038056A1 INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN 有权
标题翻译：用于改进时间依赖电介质断开的互连结构
公开(公告)号：US20120038056A1
公开(公告)日：2012-02-16
申请号：US12853537
申请日：2010-08-10
申请人： Cyril Cabral, JR. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
发明人： Cyril Cabral, JR. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/31116 , H01L21/32136 , H01L21/32139 , H01L21/76804 , H01L21/76877 , H01L21/76885 , H01L23/5283 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.
摘要翻译：本公开提供了形成到电气设备的互连的方法。在一个实施例中，形成互连的方法包括在衬底上提供器件层，其中所述器件层包括至少一个电器件，在所述至少一个电器件上的入口电介质，以及与所述至少一个电器件电连接的触点所述至少一个电气设备。在器件层上形成互连金属层，并且在互连金属层的一部分上形成含钽蚀刻掩模。蚀刻互连金属层以提供与至少一个电气设备连通的梯形互连。梯形互连具有与器件层接触的第一表面，其具有比与含钽蚀刻掩模接触的梯形互连的第二表面更大的宽度。

8. 发明申请

US20130020183A1 Silicide Micromechanical Device and Methods to Fabricate Same 有权
标题翻译：硅化物微机械装置及其制造方法
公开(公告)号：US20130020183A1
公开(公告)日：2013-01-24
申请号：US13625294
申请日：2012-09-24
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H59/00
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material.
摘要翻译：小型化机电开关包括具有触点的可移动部分，该触点构造成当开关被致动时使得两个静止点之间的电连接。至少接触由完全硅化的材料组成。一种结构包括形成在绝缘体层上的硅层和至少部分地形成在硅层内的微机电开关。微机械开关具有导电结构，并且其中导电结构的至少电接触部分由完全硅化材料构成。

9. 发明申请

US20120318649A1 Silicide Micromechanical Device and Methods to Fabricate Same 有权
标题翻译：硅化物微机械装置及其制造方法
公开(公告)号：US20120318649A1
公开(公告)日：2012-12-20
申请号：US13164126
申请日：2011-06-20
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H57/00 , H01L21/285
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction.
摘要翻译：公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。该方法包括提供设置在设置在硅衬底上的绝缘层上的硅层; 从所述绝缘层释放所述硅层的一部分，使得其至少部分地悬挂在所述绝缘层中的空腔上; 在至少所述硅层的释放部分的至少一个表面上沉积金属（例如Pt），并且使用热处理，使用沉积的金属至少完全硅化硅层的释放部分。当整个Si元件被硅化时，该方法消除了对释放的Si元件的硅化物引起的应力。此外，在形成完全硅化材料之后，也不使用常规的湿化学蚀刻，从而减少引起硅化物腐蚀和粘性增加的可能性。

10. 发明授权

US08652969B2 High aspect ratio and reduced undercut trench etch process for a semiconductor substrate 有权
标题翻译：用于半导体衬底的高纵横比和减少的底切沟槽蚀刻工艺
公开(公告)号：US08652969B2
公开(公告)日：2014-02-18
申请号：US13281715
申请日：2011-10-26
申请人： Nicholas C. M. Fuller , Eric A. Joseph , Edmund M. Sikorski , Goh Matsuura
发明人： Nicholas C. M. Fuller , Eric A. Joseph , Edmund M. Sikorski , Goh Matsuura
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L29/0657 , H01L21/30655 , H01L21/76898
摘要： A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.
摘要翻译：在各向异性蚀刻工艺中使用氢氟烃气体作为聚合物沉积气体，其使用蚀刻剂气体和聚合物沉积气体的交替来蚀刻半导体衬底中的深沟槽。氢氟烃气体可以在半导体衬底的顶表面上与聚合物的厚度一致的厚度在沟槽的侧壁上产生厚的富碳和含氢聚合物。厚的富碳和含氢聚合物保护沟槽的侧壁，从而使硬掩模下方的底切最小化，而不降低整体速率。在一些实施例中，可以实现整体蚀刻速率的改进。

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