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    • 1. 发明授权
    • Adder tree structure digital signal processor system and method
    • 加法树结构数字信号处理器系统及方法
    • US07124162B2
    • 2006-10-17
    • US10282523
    • 2002-10-29
    • Alain CombesFranz Steininger
    • Alain CombesFranz Steininger
    • G06F7/52
    • G06F7/509
    • A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is designed with reference to the vectors to be summed. The number of full- and half-adders in each stage and the arrangement of vector inputs depends upon their characteristics. An algorithm calculates the possible tree structures and input arrangements, and selects an optimum design having a small final stage ripple adder after the last stage of the Wallace tree structure, the design being based upon the characteristics of the vector inputs. This leads to reduced propagation delay and a reduced amount of semiconductor material for implementation of the DSP.
    • 布置了诸如在数字信号处理器(DSP)中使用的Wallace树结构来求和矢量。 该结构具有多个加法器级,每个加法器级可以具有带有两个输入节点的半加法器和具有三个输入节点的全加器。 参考要求的向量设计结构。 每个阶段的全加和加法器数量以及向量输入的排列取决于它们的特性。 算法计算可能的树结构和输入布置,并且在华莱士树结构的最后阶段之后选择具有小的最后阶段波纹加法器的最优设计,该设计基于向量输入的特性。 这导致减少的传播延迟和减少的用于实现DSP的半导体材料的量。
    • 2. 发明授权
    • Method and system for executing instructions in an application-specific microprocessor
    • 用于在特定于应用程序的微处理器中执行指令的方法和系统
    • US06266807B1
    • 2001-07-24
    • US09150218
    • 1998-09-09
    • Ralph McGarityFranz SteiningerJean Casteres
    • Ralph McGarityFranz SteiningerJean Casteres
    • G06F945
    • G06F8/447
    • A method for executing instructions on an application-specific microprocessor having a machine language is described. Microcontroller-like instructions are provided in a virtual language for execution on the processor. High-level DSP-like functions are compiled into DSP-like instructions in the machine language for execution on the processor. The microcontroller-like instructions are combined with the DSP-like instructions to produce a program, the program having a virtual language portion and a machine language portion respectively. When the program is executed, the virtual language portion of the program is translated into machine language instructions, and the machine language portion of the program is directly executed, such that the application-specific microprocessor executes both the DSP-like instructions and the microcontroller-like instructions.
    • 描述用于在具有机器语言的应用特定微处理器上执行指令的方法。 虚拟语言中提供了类似微控制器的指令,用于在处理器上执行。 高级DSP类功能被编译成机器语言中类似DSP的指令,用于在处理器上执行。 类似微控制器的指令与类似DSP的指令组合以产生程序,该程序分别具有虚拟语言部分和机器语言部分。 当程序被执行时,程序的虚拟语言部分被转换为机器语言指令,并且直接执行程序的机器语言部分,使得特定应用程序的微处理器执行类DSP的指令和微控制器 - 喜欢指示
    • 5. 发明授权
    • Method for powering down a microprocessor embedded within a gate array
    • 为嵌入在门阵列内的微处理器断电的方法
    • US5304860A
    • 1994-04-19
    • US135637
    • 1993-10-12
    • Laurin R. AshbyFranz Steininger
    • Laurin R. AshbyFranz Steininger
    • G06F15/78H01L21/82H01L27/118H03K19/177
    • G06F15/7867
    • An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
    • 已经提供了允许微处理器(12),ASIC单元块(16)和外部世界之间的灵活三向接口的接口电路(14),其中微处理器和ASIC单元块被制造在门 数组(10)。 接口电路为微处理器的每个I / O引脚(22,23,24)提供电路,以允许其通过ASIC I / O焊盘(20)容易地与客户设计的ASIC单元块或外部设备进行接口。 接口电路还允许仅对ASIC单元块或微处理器和ASIC单元块的微处理器进行隔离测试。 接口电路和微处理器完全扩散并固定在门阵列内,而ASIC单元块可由客户利用来设计电路以执行客户定义的功能。
    • 9. 发明授权
    • Interface control logic for embedding a microprocessor in a gate array
    • 用于将微处理器嵌入门阵列的接口控制逻辑
    • US5347181A
    • 1994-09-13
    • US875508
    • 1992-04-29
    • Laurin R. AshbyFranz Steininger
    • Laurin R. AshbyFranz Steininger
    • G06F15/78H01L21/82H01L27/118H03K19/177
    • G06F15/7867
    • An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
    • 已经提供了允许微处理器(12),ASIC单元块(16)和外部世界之间的灵活三向接口的接口电路(14),其中微处理器和ASIC单元块被制造在门 数组(10)。 接口电路为微处理器的每个I / O引脚(22,23,24)提供电路,以允许其通过ASIC I / O焊盘(20)容易地与客户设计的ASIC单元块或外部设备进行接口。 接口电路还允许仅对ASIC单元块或微处理器和ASIC单元块的微处理器进行隔离测试。 接口电路和微处理器完全扩散并固定在门阵列内,而ASIC单元块可由客户利用来设计电路以执行客户定义的功能。