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1. 发明授权

US06266807B1 Method and system for executing instructions in an application-specific microprocessor 失效
标题翻译：用于在特定于应用程序的微处理器中执行指令的方法和系统
公开(公告)号：US06266807B1
公开(公告)日：2001-07-24
申请号：US09150218
申请日：1998-09-09
申请人： Ralph McGarity , Franz Steininger , Jean Casteres
发明人： Ralph McGarity , Franz Steininger , Jean Casteres
IPC分类号： G06F945
CPC分类号： G06F8/447
摘要： A method for executing instructions on an application-specific microprocessor having a machine language is described. Microcontroller-like instructions are provided in a virtual language for execution on the processor. High-level DSP-like functions are compiled into DSP-like instructions in the machine language for execution on the processor. The microcontroller-like instructions are combined with the DSP-like instructions to produce a program, the program having a virtual language portion and a machine language portion respectively. When the program is executed, the virtual language portion of the program is translated into machine language instructions, and the machine language portion of the program is directly executed, such that the application-specific microprocessor executes both the DSP-like instructions and the microcontroller-like instructions.
摘要翻译：描述用于在具有机器语言的应用特定微处理器上执行指令的方法。虚拟语言中提供了类似微控制器的指令，用于在处理器上执行。高级DSP类功能被编译成机器语言中类似DSP的指令，用于在处理器上执行。类似微控制器的指令与类似DSP的指令组合以产生程序，该程序分别具有虚拟语言部分和机器语言部分。当程序被执行时，程序的虚拟语言部分被转换为机器语言指令，并且直接执行程序的机器语言部分，使得特定应用程序的微处理器执行类DSP的指令和微控制器 - 喜欢指示

2. 发明授权

US07124162B2 Adder tree structure digital signal processor system and method 有权
标题翻译：加法树结构数字信号处理器系统及方法
公开(公告)号：US07124162B2
公开(公告)日：2006-10-17
申请号：US10282523
申请日：2002-10-29
申请人： Alain Combes , Franz Steininger
发明人： Alain Combes , Franz Steininger
IPC分类号： G06F7/52
CPC分类号： G06F7/509
摘要： A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is designed with reference to the vectors to be summed. The number of full- and half-adders in each stage and the arrangement of vector inputs depends upon their characteristics. An algorithm calculates the possible tree structures and input arrangements, and selects an optimum design having a small final stage ripple adder after the last stage of the Wallace tree structure, the design being based upon the characteristics of the vector inputs. This leads to reduced propagation delay and a reduced amount of semiconductor material for implementation of the DSP.
摘要翻译：布置了诸如在数字信号处理器（DSP）中使用的Wallace树结构来求和矢量。该结构具有多个加法器级，每个加法器级可以具有带有两个输入节点的半加法器和具有三个输入节点的全加器。参考要求的向量设计结构。每个阶段的全加和加法器数量以及向量输入的排列取决于它们的特性。算法计算可能的树结构和输入布置，并且在华莱士树结构的最后阶段之后选择具有小的最后阶段波纹加法器的最优设计，该设计基于向量输入的特性。这导致减少的传播延迟和减少的用于实现DSP的半导体材料的量。

3. 发明授权

US07089344B1 Integrated processor platform supporting wireless handheld multi-media devices 有权
标题翻译：支持无线手持多媒体设备的集成处理器平台
公开(公告)号：US07089344B1
公开(公告)日：2006-08-08
申请号：US09591682
申请日：2000-06-09
申请人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
发明人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
IPC分类号： G06F13/28
CPC分类号： G06F13/387 , G06F2213/3814 , Y02D10/14 , Y02D10/151
摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.
摘要翻译：直接存储器存取系统由建立直接存储器访问数据通道的直接存储器访问控制器组成，并且包括用于耦合到存储器的第一接口。第二接口用于耦合到多个节点。并且处理器耦合到直接存储器访问控制器并且耦合到第二接口，其中处理器配置直接存储器访问数据信道以在可编程选择的多个节点中的一个或多个节点和存储器之间传送数据。在一些实施例中，多个节点是要在无线多媒体手持电话中实现的多媒体处理器平台的数字信号处理器存储器和主处理器存储器。

4. 发明授权

US4300915A Process for the pyrolysis of refuse 失效
标题翻译：垃圾热解工艺
公开(公告)号：US4300915A
公开(公告)日：1981-11-17
申请号：US136900
申请日：1980-04-03
申请人： Rudiger Schmidt , Franz Steininger , Klaus Hillekamp
发明人： Rudiger Schmidt , Franz Steininger , Klaus Hillekamp
IPC分类号： C10J3/00 , C10B53/00 , C10G1/00 , C10G1/02 , C10J3/66
CPC分类号： C10B53/00 , C10G1/002 , C10G1/02 , C10J3/485 , C10J3/66 , C10J3/74 , C10J3/76 , C10J3/84 , C10J2300/0946 , C10J2300/0956 , C10J2300/0959 , C10J2300/1253 , C10J2300/1823
摘要： A process for the pyrolysis of refuse of all kinds wherein the refuse is subjected to carbonization to produce solid residues and raw carbonization gases, the residues and gases are separated, the gases are divided into two parts, one part of the gases is completely burned to produce hot flue gases, the flue gases are mixed with the second part of the raw carbonization gases, the mixture of gases is cracked in a reactor, and the cracked gases are cooled.
摘要翻译：一种用于各种垃圾热解的方法，其中垃圾经受碳化以产生固体残余物和原始碳化气体，残余物和气体被分离，气体被分成两部分，一部分气体被完全燃烧成产生热烟道气，烟道气与第二部分原始碳化气体混合，气体混合物在反应器中裂解，裂解气体被冷却。

5. 发明授权

US07281066B2 Memory access system including support for multiple bus widths 有权
标题翻译：存储器访问系统包括支持多个总线宽度
公开(公告)号：US07281066B2
公开(公告)日：2007-10-09
申请号：US11221265
申请日：2005-09-07
申请人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
发明人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
IPC分类号： G06F3/00
CPC分类号： E04F21/28 , B29C63/02 , B29L2031/005 , B65H35/0013 , B65H2701/3772 , E04F21/1657 , G06F13/385 , G06F2213/3814 , Y02D10/14 , Y02D10/151 , Y10T156/1084 , Y10T156/1343
摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.
摘要翻译：直接存储器存取系统由建立直接存储器访问数据通道的直接存储器访问控制器组成，并且包括用于耦合到存储器的第一接口。第二接口用于耦合到多个节点。并且处理器耦合到直接存储器访问控制器并且耦合到第二接口，其中处理器配置直接存储器访问数据信道以在可编程选择的多个节点中的一个或多个节点和存储器之间传送数据。在一些实施例中，多个节点是要在无线多媒体手持电话中实现的多媒体处理器平台的数字信号处理器存储器和主处理器存储器。

6. 发明申请

US20060010264A1 Integrated processor platform supporting wireless handheld multi-media devices 有权
公开(公告)号：US20060010264A1
公开(公告)日：2006-01-12
申请号：US11221265
申请日：2005-09-07
申请人： Sheila Rader , Pradeep Garani , Franz Steininger , Brian Lucas
发明人： Sheila Rader , Pradeep Garani , Franz Steininger , Brian Lucas
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： E04F21/28 , B29C63/02 , B29L2031/005 , B65H35/0013 , B65H2701/3772 , E04F21/1657 , G06F13/385 , G06F2213/3814 , Y02D10/14 , Y02D10/151 , Y10T156/1084 , Y10T156/1343
摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

7. 发明授权

US5347181A Interface control logic for embedding a microprocessor in a gate array 失效
标题翻译：用于将微处理器嵌入门阵列的接口控制逻辑
公开(公告)号：US5347181A
公开(公告)日：1994-09-13
申请号：US875508
申请日：1992-04-29
申请人： Laurin R. Ashby , Franz Steininger
发明人： Laurin R. Ashby , Franz Steininger
IPC分类号： G06F15/78 , H01L21/82 , H01L27/118 , H03K19/177
CPC分类号： G06F15/7867
摘要： An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
摘要翻译：已经提供了允许微处理器（12），ASIC单元块（16）和外部世界之间的灵活三向接口的接口电路（14），其中微处理器和ASIC单元块被制造在门数组（10）。接口电路为微处理器的每个I / O引脚（22,23,24）提供电路，以允许其通过ASIC I / O焊盘（20）容易地与客户设计的ASIC单元块或外部设备进行接口。接口电路还允许仅对ASIC单元块或微处理器和ASIC单元块的微处理器进行隔离测试。接口电路和微处理器完全扩散并固定在门阵列内，而ASIC单元块可由客户利用来设计电路以执行客户定义的功能。

8. 发明授权

US5304860A Method for powering down a microprocessor embedded within a gate array 失效
标题翻译：为嵌入在门阵列内的微处理器断电的方法
公开(公告)号：US5304860A
公开(公告)日：1994-04-19
申请号：US135637
申请日：1993-10-12
申请人： Laurin R. Ashby , Franz Steininger
发明人： Laurin R. Ashby , Franz Steininger
IPC分类号： G06F15/78 , H01L21/82 , H01L27/118 , H03K19/177
CPC分类号： G06F15/7867
摘要： An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
摘要翻译：已经提供了允许微处理器（12），ASIC单元块（16）和外部世界之间的灵活三向接口的接口电路（14），其中微处理器和ASIC单元块被制造在门数组（10）。接口电路为微处理器的每个I / O引脚（22,23,24）提供电路，以允许其通过ASIC I / O焊盘（20）容易地与客户设计的ASIC单元块或外部设备进行接口。接口电路还允许仅对ASIC单元块或微处理器和ASIC单元块的微处理器进行隔离测试。接口电路和微处理器完全扩散并固定在门阵列内，而ASIC单元块可由客户利用来设计电路以执行客户定义的功能。

9. 发明授权

US4303477A Process for the pyrolysis of waste materials 失效
标题翻译：废料热解过程
公开(公告)号：US4303477A
公开(公告)日：1981-12-01
申请号：US157260
申请日：1980-06-09
申请人： Rudiger Schmidt , Franz Steininger
发明人： Rudiger Schmidt , Franz Steininger
IPC分类号： A62D3/40 , A62D101/22 , A62D101/28 , C10B47/30 , C10B53/00 , C10B53/07 , C10B57/06 , C10B57/14 , C10B57/18
CPC分类号： A62D3/40 , C10B47/30 , C10B53/00 , C10B53/07 , C10B57/06 , A62D2101/22 , A62D2101/28 , A62D2203/10 , Y02P20/143
摘要： The emission of halogens and sulfur dioxide and the formation of water-soluble compounds of heavy metals are suppressed in the pyrolysis of waste in a carbonization zone at a temperature in the range from 300.degree. to 600.degree. C. by adding a fine-grained basic material to the waste prior to completion of the pyrolysis of the waste in the carbonization zone.
摘要翻译：在300℃〜600℃的温度范围内，在碳化区的废物热分解中抑制了卤素和二氧化硫的排放以及重金属的水溶性化合物的形成。通过添加细粒度碱在碳化区内废物热解完成之前，废物的材料。

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