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1. 发明申请

US20060010264A1 Integrated processor platform supporting wireless handheld multi-media devices 有权
公开(公告)号：US20060010264A1
公开(公告)日：2006-01-12
申请号：US11221265
申请日：2005-09-07
申请人： Sheila Rader , Pradeep Garani , Franz Steininger , Brian Lucas
发明人： Sheila Rader , Pradeep Garani , Franz Steininger , Brian Lucas
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： E04F21/28 , B29C63/02 , B29L2031/005 , B65H35/0013 , B65H2701/3772 , E04F21/1657 , G06F13/385 , G06F2213/3814 , Y02D10/14 , Y02D10/151 , Y10T156/1084 , Y10T156/1343
摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

2. 发明申请

US20060004976A1 Shared memory architecture 有权
标题翻译：共享内存架构
公开(公告)号：US20060004976A1
公开(公告)日：2006-01-05
申请号：US11220735
申请日：2005-09-07
申请人： Sheila Rader
发明人： Sheila Rader
IPC分类号： G06F12/00
CPC分类号： G06F13/1684
摘要： A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.
摘要翻译：一种具有通过对应的第一和第二数据总线耦合到虚拟通道存储器控制器的第一和第二同步存储器件的无线通信架构，以及互连虚拟通道存储器控制器与第一和第二同步存储器件的共享地址和控制总线。第一和第二同步存储器设备用共享地址总线寻址，并且第一和第二存储器位置分别经由第一和第二数据总线被访问。

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