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1. 发明授权

US07289528B2 Component interconnect with self-clocking data 有权
标题翻译：组件互连与自动时钟数据
公开(公告)号：US07289528B2
公开(公告)日：2007-10-30
申请号：US10651868
申请日：2003-08-29
申请人： Kent D. Moat , Brian G. Lucas
发明人： Kent D. Moat , Brian G. Lucas
IPC分类号： H04L12/403
CPC分类号： H04L12/403 , H04L12/40
摘要： A communication signal for transmitting a sequence of tokens over an interconnection having three wires in which each of the three wire transmits a signal corresponding to one bit of a 3-bit symbol. The tokens are determined by the transitions between the symbols. In one embodiment, RF emission is minimized and self-clocking is achieved by changing exactly one bit of a symbol at each transition. A receiver detects a transition in the signal on one of the three wires, identifies the transition from the previous and current 3-bit symbols and determines the information token associated with the transition.
摘要翻译：一种用于在具有三条线的互连件上传输一系列令牌的通信信号，其中三条线中的每一条发送对应于3位符号的一个比特的信号。令牌由符号之间的转换决定。在一个实施例中，RF发射被最小化，并且通过在每个转变处恰好改变符号的一个比特来实现自定时。接收机检测三条线之一上的信号转换，识别从先前和当前3位符号的转换，并确定与转换相关的信息令牌。

2. 发明授权

US07100019B2 Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values 失效
标题翻译：使用步幅，跳跃和跨度值来寻址分割存储器中的元素向量的方法和装置
公开(公告)号：US07100019B2
公开(公告)日：2006-08-29
申请号：US10657793
申请日：2003-09-08
申请人： James M. Norris , Philip E. May , Kent D. Moat , Raymond B. Essick, IV , Brian G. Lucas
发明人： James M. Norris , Philip E. May , Kent D. Moat , Raymond B. Essick, IV , Brian G. Lucas
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： G06F9/3552 , G06F9/30036 , G06F9/345 , G06F9/3455 , G06F9/3824 , G06F9/383 , G06F9/3877 , G06F9/3879 , G06F15/7867 , G06F15/8061
摘要： A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.
摘要翻译：一种用于在具有处理单元，输入和输出单元，程序定序器和外部接口的处理系统中计算分区存储器中的存储器地址的系统和方法。地址计算器包括诸如寄存器的一组存储元件，以及用于根据存储在存储元件中的值和先前矢量元素的地址来计算向量元素的存储器地址的算术单元。存储元件保持STRIDE，SKIP和SPAN值以及可选的TYPE值，与相同分区中的元素之间的间隔相关，连续分区中的元素间距，分区中的元素数量和向量元素的大小，分别。

3. 发明授权

US6114970A Method of assigning a device identification 失效
标题翻译：分配设备标识的方法
公开(公告)号：US6114970A
公开(公告)日：2000-09-05
申请号：US780976
申请日：1997-01-09
申请人： Allan M. Kirson , Brian G. Lucas
发明人： Allan M. Kirson , Brian G. Lucas
IPC分类号： B60R16/023 , B60R16/02 , B60R16/03 , G08G1/017 , H04J3/24 , H04L29/12 , H04M3/00 , H04Q5/22
CPC分类号： H04L61/2038 , H04L29/12254 , H04L29/1232 , H04L61/2092 , B60R16/0315
摘要： The present invention provides a method of assigning a unique device identification to an electronic device coupled into a communication architecture. Once coupled into the communication architecture a piece of globally unique identifying data is retrieved and utilized to generate a device identification which identification is then assigned to the device.
摘要翻译：本发明提供了一种将独特的设备标识分配给耦合到通信架构中的电子设备的方法。一旦耦合到通信架构中，检索并利用一块全球唯一的识别数据来产生设备标识，然后将该标识分配给设备。

4. 发明授权

US07089344B1 Integrated processor platform supporting wireless handheld multi-media devices 有权
标题翻译：支持无线手持多媒体设备的集成处理器平台
公开(公告)号：US07089344B1
公开(公告)日：2006-08-08
申请号：US09591682
申请日：2000-06-09
申请人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
发明人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
IPC分类号： G06F13/28
CPC分类号： G06F13/387 , G06F2213/3814 , Y02D10/14 , Y02D10/151
摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.
摘要翻译：直接存储器存取系统由建立直接存储器访问数据通道的直接存储器访问控制器组成，并且包括用于耦合到存储器的第一接口。第二接口用于耦合到多个节点。并且处理器耦合到直接存储器访问控制器并且耦合到第二接口，其中处理器配置直接存储器访问数据信道以在可编程选择的多个节点中的一个或多个节点和存储器之间传送数据。在一些实施例中，多个节点是要在无线多媒体手持电话中实现的多媒体处理器平台的数字信号处理器存储器和主处理器存储器。

5. 发明授权

US07415601B2 Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters 失效
标题翻译：用于使用数据有效性标签和接收器计数器消除矢量处理器中的序言和epilog指令的方法和装置
公开(公告)号：US07415601B2
公开(公告)日：2008-08-19
申请号：US10652135
申请日：2003-08-29
申请人： Philip E. May , Raymond B. Essick, IV , Brian G. Lucas , Kent D. Moat , James M. Norris
发明人： Philip E. May , Raymond B. Essick, IV , Brian G. Lucas , Kent D. Moat , James M. Norris
IPC分类号： G06F9/30
CPC分类号： G06F9/3889 , G06F9/30036 , G06F9/30105 , G06F9/325 , G06F9/3824 , G06F9/3859
摘要： A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor. When a specified number of data values have been produced by a particular sink, no more data values are produced by that sink. The instructions for the pipelined loop body may be repeated, without alteration, to eliminate prolog and epilog instructions.
摘要翻译：用于消除向量处理器中的序言和外延指令的方法和装置。为了消除序言，矢量处理器的功能单元具有至少一个用于接收标记有数据有效性标签的输入数据值的输入和用于输出用数据有效性标签标记的中间结果的输出。数据有效性标签表示数据的有效性。在执行循环之前，数据有效性标签被设置为指示相关联的数据值无效。在执行循环体期间，功能单元检查输入数据的有效性。如果所有输入数据值都有效，则执行功能操作，设置相应的数据有效性标签以指示结果有效。如果任何输入数据值无效，则将结果的数据有效性标签设置为指示结果无效。为了消除epilog，迭代计数器与向量处理器的每个宿单元相关联。当特定接收器产生指定数量的数据值时，该接收器不会产生更多的数据值。流水线回路体的指令可以重复进行，而无需改变，以消除序言和epilog指令。

6. 发明授权

US07281066B2 Memory access system including support for multiple bus widths 有权
标题翻译：存储器访问系统包括支持多个总线宽度
公开(公告)号：US07281066B2
公开(公告)日：2007-10-09
申请号：US11221265
申请日：2005-09-07
申请人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
发明人： Sheila M. Rader , Pradeep Garani , Franz Steininger , Brian G. Lucas
IPC分类号： G06F3/00
CPC分类号： E04F21/28 , B29C63/02 , B29L2031/005 , B65H35/0013 , B65H2701/3772 , E04F21/1657 , G06F13/385 , G06F2213/3814 , Y02D10/14 , Y02D10/151 , Y10T156/1084 , Y10T156/1343
摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.
摘要翻译：直接存储器存取系统由建立直接存储器访问数据通道的直接存储器访问控制器组成，并且包括用于耦合到存储器的第一接口。第二接口用于耦合到多个节点。并且处理器耦合到直接存储器访问控制器并且耦合到第二接口，其中处理器配置直接存储器访问数据信道以在可编程选择的多个节点中的一个或多个节点和存储器之间传送数据。在一些实施例中，多个节点是要在无线多媒体手持电话中实现的多媒体处理器平台的数字信号处理器存储器和主处理器存储器。

7. 发明授权

US5854920A Method and apparatus for manipulating a carry/borrow bit to numerically adjust and immediate value of an instruction during execution 失效
标题翻译：用于在执行期间操纵进位/借位位以对指令进行数值调整和立即值的方法和装置
公开(公告)号：US5854920A
公开(公告)日：1998-12-29
申请号：US835371
申请日：1997-04-07
申请人： Brian G. Lucas , William C. Moyer
发明人： Brian G. Lucas , William C. Moyer
IPC分类号： G06F9/302 , G06F9/318
CPC分类号： G06F9/3001 , G06F9/30167 , G06F9/30181
摘要： Method and apparatus for adjusting the range of a data processor instruction field for a data processor (10). The present invention allows the range of a data processor instruction field to be adjusted without requiring decode of the instruction field and without requiring the instruction field value to be modified. In one embodiment, a data processor (10) uses the value of the carry-in/borrow bit (60) provided to an arithmetic unit (30) to selectively adjust the range of the immediate data operand for certain instructions, such as, for example, add immediate (ADDI) and subtract immediate (SUBI).
摘要翻译：用于调整数据处理器（10）的数据处理器指令字段的范围的方法和装置。本发明允许调整数据处理器指令字段的范围，而不需要对指令字段进行解码，而不需要修改指令字段值。在一个实施例中，数据处理器（10）使用提供给算术单元（30）的进位/借位位（60）的值来选择性地调整特定指令的立即数据操作数的范围，例如，例如，立即添加（ADDI）并减去立即（SUBI）。

8. 发明申请

US20080250499A1 Method and Apparatus for Reducing Buffer Overflow Exploits by Computer Viruses 审中-公开
标题翻译：用于减少计算机病毒的缓冲区溢出漏洞的方法和装置
公开(公告)号：US20080250499A1
公开(公告)日：2008-10-09
申请号：US11694672
申请日：2007-03-30
申请人： Kent D. Moat , Ronald F. Buskey , Brian G. Lucas
发明人： Kent D. Moat , Ronald F. Buskey , Brian G. Lucas
IPC分类号： G06F21/00
CPC分类号： G06F21/566
摘要： Buffer overflow exploits in a computer are reduced by encoding linkage information associated with a subroutine, following a call to the subroutine from an application executing on the computer. The encoded linkage information is stored at a first address in a run-time stack in a memory of the computer. Upon exit from the subroutine, the value stored at the first address in the run-time stack is retrieved and decoded to obtain decoded linkage information. Execution of the application continues in accordance with the decoded linkage information. Subroutine data written to the stack is not encoded.
摘要翻译：在从计算机上执行的应用程序调用子程序之后，通过编码与子程序相关联的链接信息来减少计算机中的缓冲区溢出漏洞利用。编码的链接信息被存储在计算机的存储器中的运行时栈中的第一地址处。在从子程序退出时，检索并解码存储在运行时堆栈中的第一地址处的值，以获得解码的链接信息。应用程序的执行根据解码的链接信息继续。写入堆栈的子程序数据不进行编码。

9. 发明授权

US07290122B2 Dataflow graph compression for power reduction in a vector processor 有权
标题翻译：用于矢量处理器中功率降低的数据流图压缩
公开(公告)号：US07290122B2
公开(公告)日：2007-10-30
申请号：US10652134
申请日：2003-08-29
申请人： Philip E. May , Brian G. Lucas , Kent D. Moat
发明人： Philip E. May , Brian G. Lucas , Kent D. Moat
IPC分类号： G06F9/308 , G06F15/18
CPC分类号： G06F9/3853 , G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F9/3017 , G06F9/3885 , Y02D10/14 , Y02D10/171
摘要： A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. The sequence of instructions for a loop is compressed by identifying a set of aligned fields that contain NOP instructions in all of the control words of the sequence. The sequence of control words is then modified by removing the fields of the identified aligned set containing NOP instructions and adding an identifier that identifies the set of fields removed. The sequence of control words is processed by fetching the identifier at the start the loop, then, for each control word in the sequence, fetching a control word and reconstructing the corresponding uncompressed control word by inserting NOP instructions into the compressed control word as indicated by the identifier. The identifier may be a bit mask and may used to disable memory units and processing elements for the duration of the loop to reduce power consumption by the processor.
摘要翻译：一种用于由多指令控制字控制的处理器中的功率降低的方法和装置。多指令控制字包括多个有序字段，每个有序字段包含用于处理器的元素的指令。通过在序列的所有控制字中识别包含NOP指令的一组对齐的字段来压缩循环的指令序列。然后通过去除包含NOP指令的所识别的对齐集合的字段来添加控制字的序列，并添加标识删除的字段的标识符。控制字的序列通过在循环开始时取出标识符来处理，然后，对于序列中的每个控制字，通过将NOP指令插入到压缩控制字中来获取控制字并重建相应的未压缩控制字，如标识符。标识符可以是位掩码，并且可以用于在循环的持续时间内禁用存储器单元和处理元件以减少处理器的功耗。

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