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1. 发明授权

US06828627B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06828627B2
公开(公告)日：2004-12-07
申请号：US10742952
申请日：2003-12-23
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

2. 发明授权

US06703669B1 Semiconductor device having serially connected memory cell transistors provided between two current terminals 有权
标题翻译：具有串联连接的存储单元晶体管的半导体器件设置在两个电流端子之间
公开(公告)号：US06703669B1
公开(公告)日：2004-03-09
申请号：US09714228
申请日：2000-11-17
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

3. 发明申请

US20050073008A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050073008A1
公开(公告)日：2005-04-07
申请号：US10993448
申请日：2004-11-22
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L23/62
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

4. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

5. 发明授权

US06828648B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06828648B2
公开(公告)日：2004-12-07
申请号：US10655122
申请日：2003-09-04
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L2900
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

6. 发明授权

US06639296B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06639296B2
公开(公告)日：2003-10-28
申请号：US09882666
申请日：2001-06-15
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L2900
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

7. 发明授权

US06274434B1 Method of making memory cell with shallow trench isolation 失效
标题翻译：制造具有浅沟槽隔离的存储单元的方法
公开(公告)号：US06274434B1
公开(公告)日：2001-08-14
申请号：US09437986
申请日：1999-11-10
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

8. 发明授权

US06413809B2 Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench 失效
标题翻译：制造具有嵌入在沟槽中的元件隔离绝缘膜的非易失性存储器的方法
公开(公告)号：US06413809B2
公开(公告)日：2002-07-02
申请号：US09800914
申请日：2001-03-08
申请人： Takuya Nakamura , Naoki Koido , Hirohisa Iizuka , Kazuhito Narita , Seiichi Aritome , Fumitaka Arai
发明人： Takuya Nakamura , Naoki Koido , Hirohisa Iizuka , Kazuhito Narita , Seiichi Aritome , Fumitaka Arai
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
摘要翻译：半导体器件具有半导体衬底，在从所述半导体衬底的表面突出的状态下嵌入形成在所述半导体衬底中的沟槽中的元件隔离绝缘膜和设置在由所述元件隔离包围的区域中的栅电极的晶体管绝缘膜，并且包含在嵌入所述元件隔离绝缘膜之前通过栅极绝缘膜沉积的栅电极，并且所述元件隔离绝缘膜的上边缘角被选择性地凹入。在这样构成的半导体器件中，元件隔离绝缘膜的上边缘角在栅电极的图案化处理之前是凹进的，从而防止了在栅电极的图案化处理中栅电极的一部分未被蚀刻的情况。

9. 发明授权

US06222225B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：具有嵌入元件隔离膜的半导体器件
公开(公告)号：US06222225B1
公开(公告)日：2001-04-24
申请号：US09405838
申请日：1999-09-27
申请人： Takuya Nakamura , Naoki Koido , Hirohisa Iizuka , Kazuhito Narita , Seiichi Aritome , Fumitaka Arai
发明人： Takuya Nakamura , Naoki Koido , Hirohisa Iizuka , Kazuhito Narita , Seiichi Aritome , Fumitaka Arai
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.
摘要翻译：半导体器件具有半导体衬底，在从所述半导体衬底的表面突出的状态下嵌入形成在所述半导体衬底中的沟槽中的元件隔离绝缘膜和设置在由所述元件隔离包围的区域中的栅电极的晶体管绝缘膜，并且包含在嵌入所述元件隔离绝缘膜之前通过栅极绝缘膜沉积的栅电极，并且所述元件隔离绝缘膜的上边缘角被选择性地凹入。在这样构成的半导体器件中，元件隔离绝缘膜的上边缘角在栅电极的图案化处理之前是凹进的，从而防止了在栅电极的图案化处理中栅电极的一部分未被蚀刻的情况。

10. 发明授权

US07064375B2 Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof 失效
标题翻译：具有栅电极和扩散层的半导体存储器件及其制造方法
公开(公告)号：US07064375B2
公开(公告)日：2006-06-20
申请号：US10602595
申请日：2003-06-25
申请人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
发明人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.
摘要翻译：一种半导体存储器件，包括具有第一栅电极，第一扩散层和第二扩散层的第一存储单元; 连接到第一存储单元的第一扩散层的第一接触层; 连接到所述第一接触层的第二接触层; 第二存储单元，具有第二栅电极，第三扩散层和第四扩散层，第二存储单元的第二栅电极与第一存储单元的第一栅极电连接，第一和第二存储单元布置在垂直于第一位线的方向; 以及与第一存储单元的第二扩散层和第二存储单元的第四扩散层共同连接的导电层，导电层的高度与第一接触层的高度基本上共面。

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