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1. 发明授权

US06828627B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06828627B2
公开(公告)日：2004-12-07
申请号：US10742952
申请日：2003-12-23
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

2. 发明授权

US06703669B1 Semiconductor device having serially connected memory cell transistors provided between two current terminals 有权
标题翻译：具有串联连接的存储单元晶体管的半导体器件设置在两个电流端子之间
公开(公告)号：US06703669B1
公开(公告)日：2004-03-09
申请号：US09714228
申请日：2000-11-17
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

3. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

4. 发明授权

US06828648B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06828648B2
公开(公告)日：2004-12-07
申请号：US10655122
申请日：2003-09-04
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L2900
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

5. 发明申请

US20050073008A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050073008A1
公开(公告)日：2005-04-07
申请号：US10993448
申请日：2004-11-22
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L23/62
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

6. 发明授权

US06639296B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06639296B2
公开(公告)日：2003-10-28
申请号：US09882666
申请日：2001-06-15
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L2900
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

7. 发明授权

US06274434B1 Method of making memory cell with shallow trench isolation 失效
标题翻译：制造具有浅沟槽隔离的存储单元的方法
公开(公告)号：US06274434B1
公开(公告)日：2001-08-14
申请号：US09437986
申请日：1999-11-10
申请人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
发明人： Naoki Koido , Riichiro Shirota , Hirohisa Iizuka
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
摘要翻译：在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状通过沉积绝缘体嵌入在沟槽中。

8. 发明授权

US6117729A Nonvolatile semiconductor storage device and its manufacturing method 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US6117729A
公开(公告)日：2000-09-12
申请号：US97152
申请日：1998-06-12
申请人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
发明人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.
摘要翻译：用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置多个NAND存储器单元。用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。

9. 发明申请

US20060157801A1 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060157801A1
公开(公告)日：2006-07-20
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

10. 发明授权

US06828624B1 Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough 失效
标题翻译：被绝缘膜覆盖的非易失性半导体存储器件，其难以氧化剂通过
公开(公告)号：US06828624B1
公开(公告)日：2004-12-07
申请号：US09556777
申请日：2000-04-25
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.
摘要翻译：非易失性半导体存储器件包括：与第一元件区域接触的元件隔离区域，覆盖存储单元的绝缘膜，外围晶体管和元件隔离区域，设置在第一元件区域的表面上的层间绝缘膜绝缘膜和设置在层间绝缘膜和绝缘膜中的接触孔。层间绝缘膜含有与绝缘膜不同的绝缘体。接触孔到达存储单元的源极和漏极扩散层中的至少一个并且与元件隔离区域重叠。绝缘膜含有与元件隔离区不同的绝缘体，绝缘膜比氧化硅膜更难以通过氧化剂。绝缘膜的表面被氧化。

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