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1. 发明授权

US5999480A Dynamic random-access memory having a hierarchical data path 有权
标题翻译：具有分层数据路径的动态随机存取存储器
公开(公告)号：US5999480A
公开(公告)日：1999-12-07
申请号：US167259
申请日：1998-10-06
申请人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.
摘要翻译：一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本相同的1M位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。

2. 发明授权

US5901105A Dynamic random access memory having decoding circuitry for partial memory blocks 失效
标题翻译：具有用于部分存储器块的解码电路的动态随机存取存储器
公开(公告)号：US5901105A
公开(公告)日：1999-05-04
申请号：US869035
申请日：1997-06-05
申请人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.
摘要翻译：公开了一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，它们集中和/或单独地证明了在诸如密度，功耗，速度和冗余度之类的考虑方面是有利和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本上相同的1兆位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了各种前置和/或后封装选项，以实现大量多功能性，冗余性和设计经济性。所公开的设备的可编程选项可通过激光熔丝和电熔丝两者来编程。在RAS链中，提供电路用于在存储器访问期间模拟字线和数字线的RC时间常数行为，使得可以优化存储器访问周期时间。测试数据压缩电路优化了测试阵列中每个单元的过程。片上拓扑电路简化了器件的测试。

3. 发明授权

US07404124B2 On-chip sampling circuit and method 失效
标题翻译：片上采样电路及方法
公开(公告)号：US07404124B2
公开(公告)日：2008-07-22
申请号：US11712040
申请日：2007-02-28
申请人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
发明人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.
摘要翻译：通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。由于与摘要相关的规则，本摘要不应用于索赔的构建。

4. 发明申请

US20070168796A1 On-chip sampling circuit and method 失效
公开(公告)号：US20070168796A1
公开(公告)日：2007-07-19
申请号：US11712041
申请日：2007-02-28
申请人： Chris Martin , James Johnson , Troy Manning , Brent Keeth
发明人： Chris Martin , James Johnson , Troy Manning , Brent Keeth
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

5. 发明申请

US20050172095A1 Dual edge command in DRAM 有权
标题翻译： DRAM中的双边沿命令
公开(公告)号：US20050172095A1
公开(公告)日：2005-08-04
申请号：US10767555
申请日：2004-01-29
申请人： Joo Choi , Troy Manning , Brent Keeth
发明人： Joo Choi , Troy Manning , Brent Keeth
IPC分类号： G06F12/00 , G11C7/10
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
摘要翻译：一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

6. 发明申请

US20050122814A1 Memory device and method having data path with multiple prefetch I/O configurations 失效
公开(公告)号：US20050122814A1
公开(公告)日：2005-06-09
申请号：US11030844
申请日：2005-01-07
申请人： Brent Keeth , Brian Johnson , Troy Manning
发明人： Brent Keeth , Brian Johnson , Troy Manning
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

7. 发明申请

US20050047228A1 Method and system for selecting redundant rows and columns of memory cells 失效
标题翻译：用于选择存储单元的冗余行和列的方法和系统
公开(公告)号：US20050047228A1
公开(公告)日：2005-03-03
申请号：US10966746
申请日：2004-10-15
申请人： Brent Keeth , Troy Manning , Chris Martin , Ebrahim Hargan
发明人： Brent Keeth , Troy Manning , Chris Martin , Ebrahim Hargan
IPC分类号： G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/848
摘要： A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a column address decoder to an array of memory cells. The system and method also includes a fuse banks for programming respective addresses of up to two defective columns that are to be repaired. The programmed addresses are applied to a defective column decoder that determines which column select signal(s) should be shifted downwardly and which column select signal(s) should be shifted upwardly. The column select steering circuit responds to signals from the defective column decoder to shift the column select signals downwardly or upwardly. The column select signal for the lowest column is shifted downwardly to a redundant column, and the column select signal for the highest column is shifted upwardly to a redundant column.
摘要翻译：用于选择存储器件的冗余行和列的系统和方法包括：列选择转向电路，用于将列选择信号从列地址解码器耦合到存储器单元阵列。该系统和方法还包括用于编程待修复的多达两个缺陷列的相应地址的熔丝组。编程的地址被应用于有缺陷的列解码器，该解码器确定哪个列选择信号应该被向下移位，哪个列选择信号应向上移位。列选择转向电路响应来自故障列解码器的信号，以向下或向上移动列选择信号。最低列的列选择信号向下移动到冗余列，最高列的列选择信号向上移动到冗余列。

8. 发明申请

US20060236170A1 On-chip sampling circuit and method 有权
标题翻译：片上采样电路及方法
公开(公告)号：US20060236170A1
公开(公告)日：2006-10-19
申请号：US11109535
申请日：2005-04-19
申请人： Chris Martin , James Johnson , Troy Manning , Brent Keeth
发明人： Chris Martin , James Johnson , Troy Manning , Brent Keeth
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.
摘要翻译：通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。由于与摘要相关的规则，本摘要不应用于索赔的构建。

9. 发明申请

US20080089158A1 Memory device and method having data path with multiple prefetch I/O configurations 失效
标题翻译：具有多个预取I / O配置的数据路径的存储器件和方法
公开(公告)号：US20080089158A1
公开(公告)日：2008-04-17
申请号：US11999383
申请日：2007-12-04
申请人： Brent Keeth , Brian Johnson , Troy Manning
发明人： Brent Keeth , Brian Johnson , Troy Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
摘要翻译：存储器件可以在高模式或低速模式下操作。在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线终端。在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个巴士总站。

10. 发明申请

US20080037342A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 有权
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：US20080037342A1
公开(公告)日：2008-02-14
申请号：US11876477
申请日：2007-10-22
申请人： Chris Martin , Troy Manning , Brent Keeth
发明人： Chris Martin , Troy Manning , Brent Keeth
IPC分类号： G11C7/00 , G11C17/18
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

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