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1. 发明申请

US20050190635A1 Memory device having conditioning output data 有权
标题翻译：具有调节输出数据的存储器件
公开(公告)号：US20050190635A1
公开(公告)日：2005-09-01
申请号：US10789190
申请日：2004-02-27
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： G11C7/10 , H04L13/10
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/1066 , G11C7/1069
摘要： A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both of the condition data and the memory data to the same data lines at different time intervals. The condition data is transferred at one time interval. The memory data is transferred at another time interval. Transferring the conditioning data to the data lines improves the accuracy of the transfer of the memory data at the data lines.
摘要翻译：存储器件具有用于存储存储器数据的存储器阵列，用于存储调节数据的调节数据存储单元和用于传送数据的数据线。在存储器操作期间，存储器件以不同的时间间隔将条件数据和存储器数据两者传送到相同的数据线。条件数据以一个时间间隔传送。存储器数据以另一时间间隔传送。将调节数据传送到数据线可以提高数据线上存储器数据传输的准确性。

2. 发明授权

US08539312B2 Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system 有权
标题翻译：使用存储器件的存储器系统和方法使用数据编码与逻辑管芯堆叠，并且系统使用存储器系统
公开(公告)号：US08539312B2
公开(公告)日：2013-09-17
申请号：US13371045
申请日：2012-02-10
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： G06F11/00
CPC分类号： G06F11/1625 , G06F11/10
摘要： A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.
摘要翻译：一种使用至少一个存储器件的存储器系统和方法，其通过互连（例如通过硅通孔）堆叠并耦合到逻辑管芯。一个这样的逻辑管芯包括产生与写入数据相对应的错误检查和校正（“ECC”）位的ECC系统。写入数据以包含多个并行数据位的串行突发的分组发送到存储器设备裸片。通过与通过数据耦合的通路不同的硅通孔将ECC位传送到存储器件管芯。这样的逻辑管芯还可以包括使用DBI算法对写入数据进行编码的数据总线反转（“DBI”）系统，并且向存储器装置发送指示写入数据是否被反转的骰子DBI位。当DBI位未被用于传送ECC位时，通过与ECC位共享的硅通孔来发送DBI位。

3. 发明申请

US20120144276A1 MEMORY SYSTEM AND METHOD USING A MEMORY DEVICE DIE STACKED WITH A LOGIC DIE USING DATA ENCODING, AND SYSTEM USING THE MEMORY SYSTEM 有权
标题翻译：使用使用数据编码的逻辑模块和使用存储器系统的系统堆叠的存储器件的存储器系统和方法
公开(公告)号：US20120144276A1
公开(公告)日：2012-06-07
申请号：US13371045
申请日：2012-02-10
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1625 , G06F11/10
摘要： A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.
摘要翻译：一种使用至少一个存储器件的存储器系统和方法，其通过互连（例如通过硅通孔）堆叠并耦合到逻辑管芯。一个这样的逻辑管芯包括产生与写入数据相对应的错误检查和校正（“ECC”）位的ECC系统。写入数据以包含多个并行数据位的串行突发的分组发送到存储器设备裸片。通过与通过数据耦合的通路不同的硅通孔将ECC位传送到存储器件管芯。这样的逻辑管芯还可以包括使用DBI算法对写入数据进行编码的数据总线反转（“DBI”）系统，并且向存储器装置发送指示写入数据是否被反转的骰子DBI位。当DBI位未被用于传送ECC位时，通过与ECC位共享的硅通孔来发送DBI位。

4. 发明申请

US20090316501A1 MEMORY MALFUNCTION PREDICTION SYSTEM AND METHOD 有权
标题翻译：存储器故障预测系统及方法
公开(公告)号：US20090316501A1
公开(公告)日：2009-12-24
申请号：US12141716
申请日：2008-06-18
申请人： Layne Bunker , Ebrahim Hargan
发明人： Layne Bunker , Ebrahim Hargan
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/42 , G06F11/1004 , G06F11/1068 , G11C29/4401 , G11C29/50 , G11C29/50016 , G11C29/52 , G11C29/70 , G11C2029/0411
摘要： A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.
摘要翻译：存储器故障预测系统和方法，例如通过降低行的刷新率来顺序地对阵列中的每一行存储器单元进行应力的系统和方法。在这样做之前，存储在行中的数据可以被复制到保持行，并且可以生成和存储数据的CRC值。测试后，可以读取存储在被测试行中的数据，然后可以生成数据的CRC值。这个经过测试的CRC值可以与存储的预测CRC值进行比较。在匹配的情况下，该行可以被认为正常工作，然后可以测试下一行。如果CRC值不匹配，则可以认为该行的预测故障存在，并且可以采取纠正措施，诸如通过用冗余的存储器单元行代替修复该行。

5. 发明申请

US20070257719A1 DEVICES AND METHODS FOR CONTROLLING A SLEW RATE OF A SIGNAL LINE 失效
标题翻译：用于控制信号线的短路速率的装置和方法
公开(公告)号：US20070257719A1
公开(公告)日：2007-11-08
申请号：US11778469
申请日：2007-07-16
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： H03K5/12
CPC分类号： H03K5/12 , H03K5/01
摘要： In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.
摘要翻译：在本发明的一个方面，公开了一种减少信号线上符号间干扰的方法。状态机记录在线上传输的先前位。如果线路上的位在几个时钟周期内是静态的，则转换速率将会增加，以便于在下一个时钟周期内正确读取该位。如果线路上的位对于以前的位是动态的，则转换速率将是较低的转换速率，以避免相邻线路之间的串扰。

6. 发明申请

US20060248415A1 MEMORY DEVICE HAVING CONDITIONING OUTPUT DATA 有权
标题翻译：具有调节输出数据的存储器件
公开(公告)号：US20060248415A1
公开(公告)日：2006-11-02
申请号：US11457298
申请日：2006-07-13
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/1066 , G11C7/1069
摘要： Some embodiments of the invention include a memory device having a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both the condition data and the memory data to the data lines at different time intervals. The condition data is transferred at one time interval. The memory data is transferred at another time interval. Other embodiments are described and claimed.
摘要翻译：本发明的一些实施例包括具有用于存储存储器数据的存储器阵列的存储器件，用于存储调节数据的调节数据存储单元和用于传送数据的数据线。在存储器操作期间，存储器件以不同的时间间隔将条件数据和存储器数据传送到数据线。条件数据以一个时间间隔传送。存储器数据以另一时间间隔传送。描述和要求保护其他实施例。

7. 发明申请

US20050047228A1 Method and system for selecting redundant rows and columns of memory cells 失效
标题翻译：用于选择存储单元的冗余行和列的方法和系统
公开(公告)号：US20050047228A1
公开(公告)日：2005-03-03
申请号：US10966746
申请日：2004-10-15
申请人： Brent Keeth , Troy Manning , Chris Martin , Ebrahim Hargan
发明人： Brent Keeth , Troy Manning , Chris Martin , Ebrahim Hargan
IPC分类号： G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/848
摘要： A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a column address decoder to an array of memory cells. The system and method also includes a fuse banks for programming respective addresses of up to two defective columns that are to be repaired. The programmed addresses are applied to a defective column decoder that determines which column select signal(s) should be shifted downwardly and which column select signal(s) should be shifted upwardly. The column select steering circuit responds to signals from the defective column decoder to shift the column select signals downwardly or upwardly. The column select signal for the lowest column is shifted downwardly to a redundant column, and the column select signal for the highest column is shifted upwardly to a redundant column.
摘要翻译：用于选择存储器件的冗余行和列的系统和方法包括：列选择转向电路，用于将列选择信号从列地址解码器耦合到存储器单元阵列。该系统和方法还包括用于编程待修复的多达两个缺陷列的相应地址的熔丝组。编程的地址被应用于有缺陷的列解码器，该解码器确定哪个列选择信号应该被向下移位，哪个列选择信号应向上移位。列选择转向电路响应来自故障列解码器的信号，以向下或向上移动列选择信号。最低列的列选择信号向下移动到冗余列，最高列的列选择信号向上移动到冗余列。

8. 发明授权

US08127204B2 Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system 有权
标题翻译：使用存储器件的存储器系统和方法使用数据编码与逻辑管芯堆叠，并且系统使用存储器系统
公开(公告)号：US08127204B2
公开(公告)日：2012-02-28
申请号：US12192796
申请日：2008-08-15
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： G06F11/00
CPC分类号： G06F11/1625 , G06F11/10
摘要： A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.
摘要翻译：一种使用至少一个存储器件的存储器系统和方法，其通过互连（例如通过硅通孔）堆叠并耦合到逻辑管芯。一个这样的逻辑管芯包括产生与写入数据相对应的错误检查和校正（“ECC”）位的ECC系统。写入数据以包含多个并行数据位的串行突发的分组发送到存储器设备裸片。通过与通过数据耦合的通路不同的硅通孔将ECC位传送到存储器件管芯。这样的逻辑管芯还可以包括使用DBI算法对写入数据进行编码的数据总线反转（“DBI”）系统，并且向存储器装置发送指示写入数据是否被反转的骰子DBI位。当DBI位未被用于传送ECC位时，通过与ECC位共享的硅通孔来发送DBI位。

9. 发明授权

US07773441B2 Memory malfunction prediction system and method 有权
标题翻译：内存故障预测系统及方法
公开(公告)号：US07773441B2
公开(公告)日：2010-08-10
申请号：US12141716
申请日：2008-06-18
申请人： Layne Bunker , Ebrahim Hargan
发明人： Layne Bunker , Ebrahim Hargan
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/42 , G06F11/1004 , G06F11/1068 , G11C29/4401 , G11C29/50 , G11C29/50016 , G11C29/52 , G11C29/70 , G11C2029/0411
摘要： A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells.
摘要翻译：存储器故障预测系统和方法，例如通过降低行的刷新率来顺序地对阵列中的每一行存储器单元进行应力的系统和方法。在这样做之前，存储在行中的数据可以被复制到保持行，并且可以生成和存储数据的CRC值。测试后，可以读取存储在被测试行中的数据，然后可以生成数据的CRC值。这个经过测试的CRC值可以与存储的预测CRC值进行比较。在匹配的情况下，该行可以被认为正常工作，然后可以测试下一行。如果CRC值不匹配，则可以认为该行的预测故障存在，并且可以采取纠正措施，诸如通过用冗余的存储器单元行代替修复该行。

10. 发明申请

US20050253635A1 History-based slew rate control to reduce intersymbol interference 有权
标题翻译：基于历史的压摆率控制，以减少符号间干扰
公开(公告)号：US20050253635A1
公开(公告)日：2005-11-17
申请号：US10847199
申请日：2004-05-17
申请人： Ebrahim Hargan
发明人： Ebrahim Hargan
IPC分类号： H03K5/12
CPC分类号： H03K5/12 , H03K5/01
摘要： In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.
摘要翻译：在本发明的一个方面，公开了一种减少信号线上符号间干扰的方法。状态机记录在线上传输的先前位。如果线路上的位在几个时钟周期内是静态的，则转换速率将会增加，以便于在下一个时钟周期内正确读取该位。如果线路上的位对于以前的位是动态的，则转换速率将是较低的转换速率，以避免相邻线路之间的串扰。

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