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1. 发明授权

US5999480A Dynamic random-access memory having a hierarchical data path 有权
标题翻译：具有分层数据路径的动态随机存取存储器
公开(公告)号：US5999480A
公开(公告)日：1999-12-07
申请号：US167259
申请日：1998-10-06
申请人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.
摘要翻译：一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本相同的1M位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。

2. 发明授权

US5675549A Burst EDO memory device address counter 失效
标题翻译：突发EDO存储设备地址计数器
公开(公告)号：US5675549A
公开(公告)日：1997-10-07
申请号：US457651
申请日：1995-06-01
申请人： Adrian Ong , Paul S. Zagar , Brett L. Wiliams , Troy A. Manning
发明人： Adrian Ong , Paul S. Zagar , Brett L. Wiliams , Troy A. Manning
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/109 , G11C7/1096 , G06F2212/2022
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译：由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件。将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。

3. 发明授权

US5293342A Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：US5293342A
公开(公告)日：1994-03-08
申请号：US993929
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

4. 再颁专利

USRE35750E Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：USRE35750E
公开(公告)日：1998-03-24
申请号：US611618
申请日：1996-03-08
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

5. 发明授权

US5311481A Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：US5311481A
公开(公告)日：1994-05-10
申请号：US993934
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

6. 发明授权

US6104645A High speed global row redundancy system 失效
标题翻译：高速全局行冗余系统
公开(公告)号：US6104645A
公开(公告)日：2000-08-15
申请号：US659724
申请日：1996-06-06
申请人： Adrian Ong , Paul S. Zagar
发明人： Adrian Ong , Paul S. Zagar
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.
摘要翻译：用于在集成电路存储器芯片的整个部分内用冗余存储器行替换有缺陷的主存储器行的行修复系统。该系统包括用于给定部分中的每个冗余行的专用匹配电路。匹配电路分析输入地址信息以确定地址是否对应于该区段内的多个子阵列块中的任何一个中的特定缺陷行中的存储器位置。当检测到这样的关键地址时，匹配电路激活禁止对缺陷行进行访问并允许访问其专用冗余行的电路。

7. 发明授权

US5528539A High speed global row redundancy system 失效
公开(公告)号：US5528539A
公开(公告)日：1996-06-18
申请号：US315154
申请日：1994-09-29
申请人： Adrian Ong , Paul S. Zagar
发明人： Adrian Ong , Paul S. Zagar
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.

8. 发明授权

US08750018B2 Sense amplifier circuitry for resistive type memory 有权
标题翻译：用于电阻型存储器的感应放大器电路
公开(公告)号：US08750018B2
公开(公告)日：2014-06-10
申请号：US13488432
申请日：2012-06-04
申请人： YongSik Youn , Adrian Ong , Sooho Cha , Chan-kyung Kim
发明人： YongSik Youn , Adrian Ong , Sooho Cha , Chan-kyung Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C7/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2207/063
摘要： Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.
摘要翻译：示例实施例包括包括差分输出端子，直接耦合到预充电晶体管的第一和第二输入端子，预充电晶体管和电流调制晶体管的电阻型存储电流读出放大器电路。预充电配置提供高峰值电流，以在电流检测放大器电路的“准备”或“预充电”阶段期间为位线和参考线充电。电流调制晶体管被配置为在至少“设置”或“放大”阶段期间以饱和区域模式工作。电流调制晶体管在“设置”或“放大”级期间连续平均位线电流和参考线电流，从而提高电路的抗噪声能力。在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。

9. 发明申请

US20130027006A1 BOOST POWER CONVERTER WITH HIGH-SIDE ACTIVE DAMPING IN DISCONTINUOUS CONDUCTION MODE 有权
标题翻译：在不连续导通模式下具有高边主动阻尼的升压电源转换器
公开(公告)号：US20130027006A1
公开(公告)日：2013-01-31
申请号：US13193311
申请日：2011-07-28
申请人： Rendon Holloway , Adrian Ong , Howard Hou
发明人： Rendon Holloway , Adrian Ong , Howard Hou
IPC分类号： G05F1/10 , G05F1/00
CPC分类号： H02M3/158 , H02J1/02
摘要： A boost power converter system according to one embodiment includes an input voltage high-side node; an inductor coupled to the input voltage high-side node at a first terminal of the inductor; a power switch coupled to the inductor at a second terminal of the inductor; a drive circuit configured to control the power switch such that the boost power converter system operates in a discontinuous conduction mode when a load current drops below a critical conduction threshold; and a damping switch configured to enable current flow from the power switch at the second terminal of the inductor to the input voltage high-side node, wherein the damping switch is closed when the power switch is open and the damping switch is opened when the power switch is closed.
摘要翻译：根据一个实施例的升压功率转换器系统包括输入电压高侧节点; 电感器，其耦合到电感器的第一端处的输入电压高侧节点; 在所述电感器的第二端子处耦合到所述电感器的功率开关; 驱动电路，被配置为控制所述功率开关，使得当负载电流下降到临界导通阈值以下时，所述升压功率转换器系统工作在不连续导通模式; 以及阻尼开关，其构造成使得能够从电感器的第二端子处的电力开关到输入电压高侧节点的电流流动，其中当电源开关断开时阻尼开关闭合，并且阻尼开关在电力开关关闭。

10. 发明申请

US20070067687A1 Integrated Circuit Testing Module Configured for Set-up and Hold Time Testing 有权
标题翻译：集成电路测试模块配置用于设置和保持时间测试
公开(公告)号：US20070067687A1
公开(公告)日：2007-03-22
申请号：US11552944
申请日：2006-10-25
申请人： Adrian Ong
发明人： Adrian Ong
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31905 , G01R31/31922 , G01R31/31926 , G06F11/263 , G11C29/14 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.
摘要翻译：公开了测试集成电路的系统和方法。这些系统包括配置成在自动测试设备和要测试的集成电路之间运行的测试模块。测试界面配置为测试集成电路的时间敏感参数。测试接口包括用于产生要传送到集成电路的地址，命令和测试数据以及时钟调整组件的组件。通过调整控制要传送到集成电路的测试信号的时钟同步，可以测试设置时间和保持时间。这些系统被配置为测试各个数据信道（例如，集成电路的单独地址线）的建立时间和保持时间。

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