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    • 6. 发明授权
    • Method for designing an integrated circuit having multiple voltage domains
    • 用于设计具有多个电压域的集成电路的方法
    • US07000214B2
    • 2006-02-14
    • US10707068
    • 2003-11-19
    • Joseph A. IadanzaRaminderpal SinghSebastian T. VentroneIvan L. Wemple
    • Joseph A. IadanzaRaminderpal SinghSebastian T. VentroneIvan L. Wemple
    • G06F17/50
    • G06F17/5045
    • A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.
    • 一种用于设计具有多个电压域的集成电路的方法,包括:(a)从包含在高级设计文件中的信息,定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; (b)基于逻辑集成电路设计,优选组件文件中的信息和电压域定义文件中的信息,将逻辑集成电路设计合成为合成集成电路设计; (c)基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和(d)根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型,以确定合成的集成电路设计是否满足预定的噪声模拟目标。
    • 8. 发明授权
    • Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits
    • 在电路原理图定制设计中最佳使用直接拟合和内插模型的方法
    • US07089512B2
    • 2006-08-08
    • US10708608
    • 2004-03-15
    • Joseph A. IadanzaRaminderpal Singh
    • Joseph A. IadanzaRaminderpal Singh
    • G06F17/50
    • G06F17/5036G06F17/5081
    • A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits. The method further comprises schematically simulating a custom circuit; back annotating to a schematic circuit which of the transistors use direct-fit models and which of the transistor devices are interpolated; determining whether the transistor devices are in any of cutoff, saturation, static linear, and dynamic linear mode during simulation of the custom circuit; removing the saturation and dynamic linear mode transistor devices; back annotating the netlist to a schematic with a predetermined device state; and performing sensitivity analysis on saturation and dynamic linear mode transistor devices.
    • 一种分析和设计电路的方法,包括为晶体管器件创建一组内插模型; 为晶体管器件创建一组特征(直接拟合)模型; 分析网表中的晶体管器件,用于在该特征模型集合中进行匹配; 并提供在设计电路中使用匹配的特征模型或内插模型之一的选择。 该方法还包括示意性地模拟定制电路; 反向注释到晶体管中的哪一个使用直接拟合模型和晶体管器件中的哪些被内插的原理图电路; 在定制电路的仿真期间确定晶体管器件是否处于截止,饱和,静态线性和动态线性模式中的任何一种; 去除饱和和动态线性模式晶体管器件; 将网表注释到具有预定设备状态的原理图; 并对饱和和动态线性模式晶体管器件执行灵敏度分析。