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    • 2. 发明授权
    • Bicycle saddle
    • 自行车马鞍
    • US09216788B1
    • 2015-12-22
    • US14560617
    • 2014-12-04
    • Chung-Ying HsuChien-Shun LaiChia-Wen Lee
    • Chung-Ying HsuChien-Shun LaiChia-Wen Lee
    • B62J1/00B62J1/18B62J1/08
    • B62J1/10
    • A bicycle saddle includes a leather cushion, a rail, and an adjusting assembly. The rail has a front end provided with an upward-extending portion, and has a rear end fixed to a rear end of the leather cushion. The adjusting assembly has a bolt holder, an adjusting bolt, and an adjusting seat. The bolt holder is fixed to a front end of the leather cushion and has a through hole. The adjusting bolt is rotatably received in the through hole of the bolt holder. The adjusting seat is fixed to the upward-extending portion of the rail and is screwed and engaged with the threaded trunk of the adjusting bolt. Thereby, the saddle is unlikely to sway and remains structurally stable during cycling, and noise can be effectively reduced.
    • 自行车鞍座包括皮革衬垫,轨道和调整组件。 导轨具有设置有向上延伸部分的前端,并且其后端固定到皮革衬垫的后端。 调节组件具有螺栓保持器,调节螺栓和调节座。 螺栓保持器固定在皮革衬垫的前端,并具有通孔。 调节螺栓可旋转地容纳在螺栓保持器的通孔中。 调节座固定在轨道的向上延伸部分上,并与调整螺栓的螺纹螺纹螺纹接合。 因此,鞍座在循环期间不太可能摇摆并保持结构稳定,并且可以有效地降低噪声。
    • 5. 发明授权
    • Method for main spacer trim-back
    • 主间隔装饰方法
    • US08343867B2
    • 2013-01-01
    • US13234674
    • 2011-09-16
    • Jin-Aun NgYu-Ying HsuChi-Ju LeeSin-Hua WuBao-Ru YoungHarry-Hak-Lay Chuang
    • Jin-Aun NgYu-Ying HsuChi-Ju LeeSin-Hua WuBao-Ru YoungHarry-Hak-Lay Chuang
    • H01L21/4763
    • H01L21/823425H01L21/823468H01L21/823475
    • The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
    • 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层(或硬掩模)在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀(或修整)工艺的工艺均匀性(或控制)确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要,例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物,并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好,接触良好的硅化物提高了接触的收率,并使接触电阻达到可接受和可操作的范围。
    • 6. 发明申请
    • OUTPUT STAGE CIRCUIT FOR OUTPUTTING A DRIVING CURRENT VARYING WITH A PROCESS
    • 用于输出驱动电流变化的输出电路
    • US20120229174A1
    • 2012-09-13
    • US13099380
    • 2011-05-03
    • Chun ShiahHao-Jan YangChing-Ying Hsu
    • Chun ShiahHao-Jan YangChing-Ying Hsu
    • H03K3/00
    • H03K19/018521H03K19/09482
    • An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor.
    • 输出级电路包括第一P型金属氧化物半导体晶体管,第二P型金属氧化物半导体晶体管,N型金属氧化物半导体晶体管和电流源。 第一P型金属氧化物半导体晶体管的第三端子的电压是第一电压减去第一P型金属氧化物半导体晶体管的第一端子和第二端子之间的电压降。 N型金属氧化物半导体晶体管耦合在第一P型金属氧化物半导体晶体管的第三端子与电流源之间。 第二P型金属氧化物半导体晶体管的第二端子耦合到第一P型金属氧化物半导体晶体管的第三端子。 当N型金属氧化物半导体晶体管的第二端子接收到反冲信号时,流过第二P型金属氧化物半导体晶体管的驱动电流与第一P型金属氧化物半导体晶体管的第三端子的电压相关, 型金属氧化物半导体晶体管。
    • 10. 发明申请
    • MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS
    • 用于替换门过程的主间隔三角法
    • US20110237040A1
    • 2011-09-29
    • US12730375
    • 2010-03-24
    • Jin-Aun NGYu-Ying HSUChi-Ju LEESin-Hua WUBao-Ru YOUNGHarry-Hak-Lay CHUANG
    • Jin-Aun NGYu-Ying HSUChi-Ju LEESin-Hua WUBao-Ru YOUNGHarry-Hak-Lay CHUANG
    • H01L21/336
    • H01L21/823425H01L21/823468H01L21/823475
    • The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
    • 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层(或硬掩模)在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀(或修整)工艺的工艺均匀性(或控制)确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要,例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物,并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好,接触良好的硅化物提高了接触的收率,并使接触电阻达到可接受和可操作的范围。