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1. 发明授权

US06525398B1 Semiconductor device capable of preventing moisture-absorption of fuse area thereof 有权
标题翻译：能够防止其保险丝区域的吸湿的半导体装置
公开(公告)号：US06525398B1
公开(公告)日：2003-02-25
申请号：US09650967
申请日：2000-08-29
申请人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
发明人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
IPC分类号： H01L2900
CPC分类号： H01L23/564 , H01L21/768 , H01L23/5258 , H01L23/585 , H01L27/10814 , H01L27/10894 , H01L27/11 , H01L2924/0002 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process. In addition, the etch stop layer is also formed under the fuse opening portion so that an insulating layer remaining on the fuse line can be controlled to have a predetermined thickness when forming the fuse opening portion, thereby improving the cutting efficiency of fuses.
摘要翻译：提供了能够防止吸湿的半导体器件的保险丝区域和制造保险丝区域的方法。当形成用于防止湿气透过露出的保险丝开口部分的侧壁的保护环时，在熔丝线上形成蚀刻停止层。使用蚀刻停止层形成防护环开口部。保护环开口部分填充有用于形成多层互连布线的最上布线或钝化层的材料的材料，从而与最上面的布线或钝化层同时形成保护环。因此，可以通过简单的工艺有效地防止湿气渗透到层间绝缘层或熔断器开口部周围的层间绝缘层之间的界面。另外，在保险丝开口部分也形成有蚀刻停止层，使得在形成保险丝开口部分时，保留在熔丝线上的绝缘层可以被控制为具有预定的厚度，从而提高了保险丝的切割效率。

2. 发明授权

US5858833A Methods for manufacturing integrated circuit memory devices including trench buried bit lines 失效
标题翻译：包括沟槽埋置位线的集成电路存储器件的制造方法
公开(公告)号：US5858833A
公开(公告)日：1999-01-12
申请号：US781374
申请日：1997-01-21
申请人： Won-seong Lee , Chang-gyu Hwang
发明人： Won-seong Lee , Chang-gyu Hwang
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Integrated circuit memory devices are manufactured by forming spaced apart source and drain regions in an integrated circuit substrate, and an insulated gate on the integrated circuit substrate therebetween. An interlayer insulating layer is formed on the integrated circuit substrate, including first and second conductive pad contacts which extend therethrough and which electrically contact the source and the drain region, respectively. A trench is formed in the interlayer insulating layer, including in the second conductive pad contact. A first insulating layer is formed to line the trench, except for adjacent the second conductive pad contact. A buried bit line is formed in the trench, electrically contacting the second conductive pad contact through the first insulating layer. A second insulating layer is formed on the first insulating layer and on the buried bit line, except for adjacent the first conductive pad contact. A patterned storage electrode is formed on the second insulating layer, which electrically contacts the first conductive contact pad.
摘要翻译：通过在集成电路基板中形成间隔开的源极和漏极区域以及集成电路存储器件之间的集成电路基板上的绝缘栅极来制造集成电路存储器件。在集成电路基板上形成层间绝缘层，其中包括分别延伸通过其并与源区和漏区电接触的第一和第二导电焊盘触点。沟槽形成在层间绝缘层中，包括在第二导电焊盘触点中。除了与第二导电焊盘接触件相邻之外，形成第一绝缘层以排列沟槽。在沟槽中形成掩埋位线，使第二导电焊盘触点与第一绝缘层电接触。第二绝缘层形成在第一绝缘层和掩埋位线上，除了与第一导电焊盘接触相邻。图案化的存储电极形成在与第一导电接触焊盘电接触的第二绝缘层上。

3. 发明授权

US07517762B2 Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area 有权
标题翻译：能够防止保险丝区域吸湿的半导体装置及制造保险丝区域的方法
公开(公告)号：US07517762B2
公开(公告)日：2009-04-14
申请号：US11139906
申请日：2005-05-26
申请人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
发明人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
IPC分类号： H01L23/62 , H01L21/8242
CPC分类号： H01L23/564 , H01L21/768 , H01L23/5258 , H01L23/585 , H01L27/10814 , H01L27/10894 , H01L27/11 , H01L2924/0002 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process. In addition, the etch stop layer is also formed under the fuse opening portion so that an insulating layer remaining on the fuse line can be controlled to have a predetermined thickness when forming the fuse opening portion, thereby improving the cutting efficiency of fuses.
摘要翻译：提供了能够防止吸湿的半导体器件的保险丝区域和制造保险丝区域的方法。当形成用于防止湿气透过露出的保险丝开口部分的侧壁的保护环时，在熔丝线上形成蚀刻停止层。使用蚀刻停止层形成防护环开口部。保护环开口部分填充有用于形成多层互连布线的最上布线或钝化层的材料的材料，从而与最上面的布线或钝化层同时形成保护环。因此，可以通过简单的工艺有效地防止湿气渗透到层间绝缘层或熔断器开口部周围的层间绝缘层之间的界面。另外，在保险丝开口部分也形成有蚀刻停止层，使得在形成保险丝开口部分时，保留在熔丝线上的绝缘层可以被控制为具有预定的厚度，从而提高了保险丝的切割效率。

4. 发明授权

US06844240B2 Semiconductor device having trench isolation 有权
标题翻译：具有沟槽隔离的半导体器件
公开(公告)号：US06844240B2
公开(公告)日：2005-01-18
申请号：US09948799
申请日：2001-09-10
申请人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
发明人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： A structure having trench isolation which protects a nitride liner in the trench during subsequent plasma processing. The structure includes a trench formed in a semiconductor substrate, the trench having sidewalls and a bottom. A thermal oxide layer is formed on the bottom and sidewalls of the trench so as to remove substrate damage caused during etching of the semiconductor substrate to form the trench. A material layer is formed on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized. Then, a protection layer is formed on the oxidation barrier layer. The trench is filled with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.
摘要翻译：具有沟槽隔离的结构，其在随后的等离子体处理期间保护沟槽中的氮化物衬垫。该结构包括形成在半导体衬底中的沟槽，沟槽具有侧壁和底部。在沟槽的底部和侧壁上形成热氧化层，以消除在半导体衬底的蚀刻过程中造成的衬底损伤，形成沟槽。在热氧化物层上形成材料层，以防止沟槽的底部和侧壁被氧化。然后，在氧化阻挡层上形成保护层。沟槽相对于沟槽的底部和侧壁均匀地填充沟槽填充材料。

5. 发明申请

US20050221539A1 Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area 有权
标题翻译：能够防止保险丝区域吸湿的半导体装置及制造保险丝区域的方法
公开(公告)号：US20050221539A1
公开(公告)日：2005-10-06
申请号：US11139906
申请日：2005-05-26
申请人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
发明人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
IPC分类号： H01L27/00 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L21/8244 , H01L23/00 , H01L23/525 , H01L23/58 , H01L27/108
CPC分类号： H01L23/564 , H01L21/768 , H01L23/5258 , H01L23/585 , H01L27/10814 , H01L27/10894 , H01L27/11 , H01L2924/0002 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process. In addition, the etch stop layer is also formed under the fuse opening portion so that an insulating layer remaining on the fuse line can be controlled to have a predetermined thickness when forming the fuse opening portion, thereby improving the cutting efficiency of fuses.
摘要翻译：提供了能够防止吸湿的半导体器件的保险丝区域和制造保险丝区域的方法。当形成用于防止湿气透过露出的保险丝开口部分的侧壁的保护环时，在熔丝线上形成蚀刻停止层。使用蚀刻停止层形成防护环开口部。保护环开口部分填充有用于形成多层互连布线的最上布线或钝化层的材料的材料，从而与最上面的布线或钝化层同时形成保护环。因此，可以通过简单的工艺有效地防止湿气渗透到层间绝缘层或熔断器开口部周围的层间绝缘层之间的界面。另外，在保险丝开口部分也形成有蚀刻停止层，使得在形成保险丝开口部分时，保留在熔丝线上的绝缘层可以被控制为具有预定的厚度，从而提高了保险丝的切割效率。

6. 发明授权

US06913953B2 Semiconductor device capable of preventing moisture absorption of fuse area thereof and method for manufacturing the fuse area 有权
标题翻译：能够防止保险丝区域的吸湿的半导体装置及制造保险丝区域的方法
公开(公告)号：US06913953B2
公开(公告)日：2005-07-05
申请号：US10334745
申请日：2002-12-31
申请人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
发明人： Byung-yoon Kim , Won-seong Lee , Young-woo Park
IPC分类号： H01L27/00 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L21/8244 , H01L23/00 , H01L23/525 , H01L23/58 , H01L27/108 , H01L21/44
CPC分类号： H01L23/564 , H01L21/768 , H01L23/5258 , H01L23/585 , H01L27/10814 , H01L27/10894 , H01L27/11 , H01L2924/0002 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process. In addition, the etch stop layer is also formed under the fuse opening portion so that an insulating layer remaining on the fuse line can be controlled to have a predetermined thickness when forming the fuse opening portion, thereby improving the cutting efficiency of fuses.
摘要翻译：提供了能够防止吸湿的半导体器件的保险丝区域和制造保险丝区域的方法。当形成用于防止湿气透过露出的保险丝开口部分的侧壁的保护环时，在熔丝线上形成蚀刻停止层。使用蚀刻停止层形成防护环开口部。保护环开口部分填充有用于形成多层互连布线的最上布线或钝化层的材料的材料，从而与最上面的布线或钝化层同时形成保护环。因此，可以通过简单的工艺有效地防止湿气渗透到层间绝缘层或熔断器开口部周围的层间绝缘层之间的界面。另外，在保险丝开口部分也形成蚀刻停止层，使得在形成保险丝开口部分时，保留在熔丝线上的绝缘层可以被控制成具有预定的厚度，从而提高保险丝的切割效率。

7. 发明授权

US06607983B1 Method of processing a defect source at a wafer edge region in a semiconductor manufacturing 失效
标题翻译：在半导体制造中在晶片边缘区域处理缺陷源的方法
公开(公告)号：US06607983B1
公开(公告)日：2003-08-19
申请号：US09707353
申请日：2000-11-06
申请人： Kwang-Youl Chun , Yun-Jae Lee , Won-Seong Lee , Jeong-Hoon Oh , Kyu-Hyun Lee
发明人： Kwang-Youl Chun , Yun-Jae Lee , Won-Seong Lee , Jeong-Hoon Oh , Kyu-Hyun Lee
IPC分类号： H01L21461
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76802 , H01L21/76838 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.
摘要翻译：本发明提供一种消除或覆盖用于半导体制造的晶片边缘区域中的缺陷源的方法。在用于存储节点开口的牺牲氧化物层的蚀刻工艺期间，由于蚀刻在牺牲氧化物层上形成的光致抗蚀剂层的不均匀性，牺牲氧化物层在晶片边缘区域中具有隆起的拓扑结构。随后沉积导电层和平坦化蚀刻，导电层不期望地保留在晶片边缘区域作为缺陷源。这种导电性污染物颗粒移动，在晶片主区域引起许多问题。本发明通过两种方法去除这种缺陷源。一个是使用其曝光的光致抗蚀剂图案直接去除缺陷源。另一种是通过在随后的清洁过程中通过光致抗蚀剂图案的保护来将缺陷源固定在晶片边缘区域中。

8. 发明授权

US06399476B2 Multilayer passivation process for forming air gaps within a dielectric between interconnections 有权
标题翻译：用于在互连之间的电介质内形成气隙的多层钝化工艺
公开(公告)号：US06399476B2
公开(公告)日：2002-06-04
申请号：US09432101
申请日：1999-11-02
申请人： Jin Yang Kim , Si-Woo Lee , Won Seong Lee , Sang-Pil Sim
发明人： Jin Yang Kim , Si-Woo Lee , Won Seong Lee , Sang-Pil Sim
IPC分类号： H01C214763
CPC分类号： H01L21/7682
摘要： A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.
摘要翻译：提供了一种用于在层间电介质内形成气隙的工艺，以减少互连之间的负载电容。第一介电层沉积在间隔开的互连上。该第一电介质层在顶侧比在互连的底侧更厚地沉积。第二电介质层沉积在第一介电层上至受控的厚度，导致在互连之间形成空隙。第一电介质层的差的台阶覆盖使得容易形成气隙。互连之间的空气间隙允许整个电介质结构的介电常数降低，从而将互连线减少到线路电容，并且增加半导体器件的可能的操作速度。

9. 发明授权

US06326282B1 Method of forming trench isolation in a semiconductor device and structure formed thereby 有权
标题翻译：在半导体器件中形成沟槽隔离的方法和由此形成的结构
公开(公告)号：US06326282B1
公开(公告)日：2001-12-04
申请号：US09290890
申请日：1999-04-14
申请人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
发明人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming trench isolation which protects a nitride liner in the trench during subsequent plasma processing, by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. A trench mask is formed on a semiconductor substrate to define a trench forming region, the semiconductor substrate is etched using the trench mask to form a trench, a thermal oxide layer is formed on a bottom and sidewalls of the trench to remove substrate damage caused by the etching, a material layer is formed on the thermal oxide layer to prevent the bottom and sidewalls of the trench from being oxidized, a protection layer is formed on the oxidation barrier layer, the bottom and sidewalls of the trench are plasma processed, and the trench is then filled with a trench fill material uniformly with respect to the bottom and sidewalls.
摘要翻译：一种形成沟槽隔离的方法，通过形成诸如HTO氧化物层或LP-TEOS氧化物层的高温氧化物层，在随后的等离子体处理期间保护沟槽中的氮化物衬垫。在半导体衬底上形成沟槽掩模以限定沟槽形成区域，使用沟槽掩模蚀刻半导体衬底以形成沟槽，在沟槽的底部和侧壁上形成热氧化层，以消除由蚀刻时，在热氧化层上形成材料层以防止沟槽的底部和侧壁被氧化，在氧化阻挡层上形成保护层，等离子体处理沟槽的底部和侧壁，沟槽然后相对于底部和侧壁均匀地填充沟槽填充材料。

10. 发明授权

US06121146A Method for forming contact plugs of a semiconductor device 失效
标题翻译：用于形成半导体器件的接触插塞的方法
公开(公告)号：US06121146A
公开(公告)日：2000-09-19
申请号：US92021
申请日：1998-06-05
申请人： Bo-Un Yoon , In-Kwon Jeong , Won-Seong Lee
发明人： Bo-Un Yoon , In-Kwon Jeong , Won-Seong Lee
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/321 , H01L21/768
CPC分类号： H01L21/7684 , H01L21/76819 , H01L21/31053 , H01L21/3212
摘要： A method for forming contact plugs of a semiconductor device includes a step of forming a conductive layer on an insulating layer filling up a contact hole. The method further comprises a step of planarization-etching an upper surface of the insulating layer as well as the contact plugs, after formation of the contact plugs by etching the conductive layer using an etch-back or a CMP process until at least the upper surface of the insulating layer is exposed. Alternatively, the conductive and insulating layers are simultaneously planarization-etched using a CMP process once to form the contact plugs and planarize the upper surface of the insulating layer. With this method, a bridge between interconnections which can be generated due to a scratch of the upper surface of the insulating layer can be prevented by planarization-etching the conductive layer after filling up a contact hole with the conductive layer. Also, since the insulating layer includes a lower insulating layer and an upper insulating layer having a relatively high hardness to the lower insulating layer, high-step and low-step regions of the insulating layer formed along topology of a gate electrode or a metal interconnection are efficiently planarized. As a result, a thickness of the insulating layer can be considerably reduced.
摘要翻译：用于形成半导体器件的接触插塞的方法包括在填充接触孔的绝缘层上形成导电层的步骤。该方法还包括在通过使用回蚀刻或CMP工艺蚀刻导电层形成接触插塞之后，平坦化 - 蚀刻绝缘层的上表面以及接触插塞的步骤，直到至少上表面的绝缘层露出。或者，使用CMP处理同时对导电绝缘层进行平面蚀刻，以形成接触插塞并平坦化绝缘层的上表面。利用该方法，可以通过在与导电层填充接触孔之后对导电层进行平坦化蚀刻来防止由于绝缘层的上表面的划痕而产生的互连之间的桥。此外，由于绝缘层包括下绝缘层和对下绝缘层具有相对较高硬度的上绝缘层，所以沿着栅电极或金属互连的拓扑形成绝缘层的高阶段和低阶区有效地平坦化。结果，绝缘层的厚度可以大大降低。

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