会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Multilayer passivation process for forming air gaps within a dielectric between interconnections
    • 用于在互连之间的电介质内形成气隙的多层钝化工艺
    • US06399476B2
    • 2002-06-04
    • US09432101
    • 1999-11-02
    • Jin Yang KimSi-Woo LeeWon Seong LeeSang-Pil Sim
    • Jin Yang KimSi-Woo LeeWon Seong LeeSang-Pil Sim
    • H01C214763
    • H01L21/7682
    • A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.
    • 提供了一种用于在层间电介质内形成气隙的工艺,以减少互连之间的负载电容。 第一介电层沉积在间隔开的互连上。 该第一电介质层在顶侧比在互连的底侧更厚地沉积。 第二电介质层沉积在第一介电层上至受控的厚度,导致在互连之间形成空隙。 第一电介质层的差的台阶覆盖使得容易形成气隙。 互连之间的空气间隙允许整个电介质结构的介电常数降低,从而将互连线减少到线路电容,并且增加半导体器件的可能的操作速度。
    • 2. 发明授权
    • Semiconductor memory device having capacitor for peripheral circuit
    • 具有用于外围电路的电容器的半导体存储器件
    • US07999299B2
    • 2011-08-16
    • US12264490
    • 2008-11-04
    • Jung-Hwa LeeSi-Woo Lee
    • Jung-Hwa LeeSi-Woo Lee
    • H01L27/108
    • H01L27/10894H01L27/0207H01L27/0629H01L28/40
    • Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.
    • 提供了具有外围电路电容器的半导体存储器件。 在半导体存储器件中,第一节点电连接到外围电路区域中的多个电容器的多个下电极,以平行地连接至少一部分电容器。 第二节点电连接到外围电路区域中的电容器的多个上电极,以平行地连接至少一部分电容器。 第一节点形成在与单元阵列区域中的位线基本相同的电平上,并且由用于形成位线的相同材料形成。