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1. 发明授权

US06844240B2 Semiconductor device having trench isolation 有权
标题翻译：具有沟槽隔离的半导体器件
公开(公告)号：US06844240B2
公开(公告)日：2005-01-18
申请号：US09948799
申请日：2001-09-10
申请人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
发明人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： A structure having trench isolation which protects a nitride liner in the trench during subsequent plasma processing. The structure includes a trench formed in a semiconductor substrate, the trench having sidewalls and a bottom. A thermal oxide layer is formed on the bottom and sidewalls of the trench so as to remove substrate damage caused during etching of the semiconductor substrate to form the trench. A material layer is formed on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized. Then, a protection layer is formed on the oxidation barrier layer. The trench is filled with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.
摘要翻译：具有沟槽隔离的结构，其在随后的等离子体处理期间保护沟槽中的氮化物衬垫。该结构包括形成在半导体衬底中的沟槽，沟槽具有侧壁和底部。在沟槽的底部和侧壁上形成热氧化层，以消除在半导体衬底的蚀刻过程中造成的衬底损伤，形成沟槽。在热氧化物层上形成材料层，以防止沟槽的底部和侧壁被氧化。然后，在氧化阻挡层上形成保护层。沟槽相对于沟槽的底部和侧壁均匀地填充沟槽填充材料。

2. 发明授权

US06326282B1 Method of forming trench isolation in a semiconductor device and structure formed thereby 有权
标题翻译：在半导体器件中形成沟槽隔离的方法和由此形成的结构
公开(公告)号：US06326282B1
公开(公告)日：2001-12-04
申请号：US09290890
申请日：1999-04-14
申请人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
发明人： Young-woo Park , Yong-chul Oh , Won-Seong Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming trench isolation which protects a nitride liner in the trench during subsequent plasma processing, by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. A trench mask is formed on a semiconductor substrate to define a trench forming region, the semiconductor substrate is etched using the trench mask to form a trench, a thermal oxide layer is formed on a bottom and sidewalls of the trench to remove substrate damage caused by the etching, a material layer is formed on the thermal oxide layer to prevent the bottom and sidewalls of the trench from being oxidized, a protection layer is formed on the oxidation barrier layer, the bottom and sidewalls of the trench are plasma processed, and the trench is then filled with a trench fill material uniformly with respect to the bottom and sidewalls.
摘要翻译：一种形成沟槽隔离的方法，通过形成诸如HTO氧化物层或LP-TEOS氧化物层的高温氧化物层，在随后的等离子体处理期间保护沟槽中的氮化物衬垫。在半导体衬底上形成沟槽掩模以限定沟槽形成区域，使用沟槽掩模蚀刻半导体衬底以形成沟槽，在沟槽的底部和侧壁上形成热氧化层，以消除由蚀刻时，在热氧化层上形成材料层以防止沟槽的底部和侧壁被氧化，在氧化阻挡层上形成保护层，等离子体处理沟槽的底部和侧壁，沟槽然后相对于底部和侧壁均匀地填充沟槽填充材料。

3. 发明授权

US06607983B1 Method of processing a defect source at a wafer edge region in a semiconductor manufacturing 失效
标题翻译：在半导体制造中在晶片边缘区域处理缺陷源的方法
公开(公告)号：US06607983B1
公开(公告)日：2003-08-19
申请号：US09707353
申请日：2000-11-06
申请人： Kwang-Youl Chun , Yun-Jae Lee , Won-Seong Lee , Jeong-Hoon Oh , Kyu-Hyun Lee
发明人： Kwang-Youl Chun , Yun-Jae Lee , Won-Seong Lee , Jeong-Hoon Oh , Kyu-Hyun Lee
IPC分类号： H01L21461
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76802 , H01L21/76838 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.
摘要翻译：本发明提供一种消除或覆盖用于半导体制造的晶片边缘区域中的缺陷源的方法。在用于存储节点开口的牺牲氧化物层的蚀刻工艺期间，由于蚀刻在牺牲氧化物层上形成的光致抗蚀剂层的不均匀性，牺牲氧化物层在晶片边缘区域中具有隆起的拓扑结构。随后沉积导电层和平坦化蚀刻，导电层不期望地保留在晶片边缘区域作为缺陷源。这种导电性污染物颗粒移动，在晶片主区域引起许多问题。本发明通过两种方法去除这种缺陷源。一个是使用其曝光的光致抗蚀剂图案直接去除缺陷源。另一种是通过在随后的清洁过程中通过光致抗蚀剂图案的保护来将缺陷源固定在晶片边缘区域中。

4. 发明授权

US06121146A Method for forming contact plugs of a semiconductor device 失效
标题翻译：用于形成半导体器件的接触插塞的方法
公开(公告)号：US06121146A
公开(公告)日：2000-09-19
申请号：US92021
申请日：1998-06-05
申请人： Bo-Un Yoon , In-Kwon Jeong , Won-Seong Lee
发明人： Bo-Un Yoon , In-Kwon Jeong , Won-Seong Lee
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/321 , H01L21/768
CPC分类号： H01L21/7684 , H01L21/76819 , H01L21/31053 , H01L21/3212
摘要： A method for forming contact plugs of a semiconductor device includes a step of forming a conductive layer on an insulating layer filling up a contact hole. The method further comprises a step of planarization-etching an upper surface of the insulating layer as well as the contact plugs, after formation of the contact plugs by etching the conductive layer using an etch-back or a CMP process until at least the upper surface of the insulating layer is exposed. Alternatively, the conductive and insulating layers are simultaneously planarization-etched using a CMP process once to form the contact plugs and planarize the upper surface of the insulating layer. With this method, a bridge between interconnections which can be generated due to a scratch of the upper surface of the insulating layer can be prevented by planarization-etching the conductive layer after filling up a contact hole with the conductive layer. Also, since the insulating layer includes a lower insulating layer and an upper insulating layer having a relatively high hardness to the lower insulating layer, high-step and low-step regions of the insulating layer formed along topology of a gate electrode or a metal interconnection are efficiently planarized. As a result, a thickness of the insulating layer can be considerably reduced.
摘要翻译：用于形成半导体器件的接触插塞的方法包括在填充接触孔的绝缘层上形成导电层的步骤。该方法还包括在通过使用回蚀刻或CMP工艺蚀刻导电层形成接触插塞之后，平坦化 - 蚀刻绝缘层的上表面以及接触插塞的步骤，直到至少上表面的绝缘层露出。或者，使用CMP处理同时对导电绝缘层进行平面蚀刻，以形成接触插塞并平坦化绝缘层的上表面。利用该方法，可以通过在与导电层填充接触孔之后对导电层进行平坦化蚀刻来防止由于绝缘层的上表面的划痕而产生的互连之间的桥。此外，由于绝缘层包括下绝缘层和对下绝缘层具有相对较高硬度的上绝缘层，所以沿着栅电极或金属互连的拓扑形成绝缘层的高阶段和低阶区有效地平坦化。结果，绝缘层的厚度可以大大降低。

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