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1. 发明授权

US06399476B2 Multilayer passivation process for forming air gaps within a dielectric between interconnections 有权
标题翻译：用于在互连之间的电介质内形成气隙的多层钝化工艺
公开(公告)号：US06399476B2
公开(公告)日：2002-06-04
申请号：US09432101
申请日：1999-11-02
申请人： Jin Yang Kim , Si-Woo Lee , Won Seong Lee , Sang-Pil Sim
发明人： Jin Yang Kim , Si-Woo Lee , Won Seong Lee , Sang-Pil Sim
IPC分类号： H01C214763
CPC分类号： H01L21/7682
摘要： A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.
摘要翻译：提供了一种用于在层间电介质内形成气隙的工艺，以减少互连之间的负载电容。第一介电层沉积在间隔开的互连上。该第一电介质层在顶侧比在互连的底侧更厚地沉积。第二电介质层沉积在第一介电层上至受控的厚度，导致在互连之间形成空隙。第一电介质层的差的台阶覆盖使得容易形成气隙。互连之间的空气间隙允许整个电介质结构的介电常数降低，从而将互连线减少到线路电容，并且增加半导体器件的可能的操作速度。

2. 发明申请

US20070268749A1 Method for operating non-volatile memory device 审中-公开
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20070268749A1
公开(公告)日：2007-11-22
申请号：US11802282
申请日：2007-05-22
申请人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
发明人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0483 , G11C16/3409 , G11C16/345
摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.
摘要翻译：公开了一种操作非易失性存储器件的方法。存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

3. 发明申请

US20140353769A1 SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS 审中-公开
公开(公告)号：US20140353769A1
公开(公告)日：2014-12-04
申请号：US14463394
申请日：2014-08-19
申请人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
发明人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L29/10 , H01L27/088 , H01L29/78
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

4. 发明申请

US20070105309A1 Contactless nonvolatile memory device and method of forming the same 有权
公开(公告)号：US20070105309A1
公开(公告)日：2007-05-10
申请号：US11590620
申请日：2006-10-31
申请人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

5. 发明申请

US20060030102A1 Flash memory devices including a pass transistor and methods of forming the same 有权
标题翻译：包括传输晶体管的闪存器件及其形成方法
公开(公告)号：US20060030102A1
公开(公告)日：2006-02-09
申请号：US11021232
申请日：2004-12-23
申请人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
发明人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.
摘要翻译：闪存集成电路器件包括集成电路基板。集成电路基板上的单元阵列包括多个单元晶体管。位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。一个或多个第二传输晶体管耦合到第一传输晶体管。第二传输晶体管具有第二扩散结构。第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

6. 发明申请

US20140159158A1 Semiconductor Devices 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140159158A1
公开(公告)日：2014-06-12
申请号：US14100054
申请日：2013-12-09
申请人： Ho-Jun Kim , Chulhong Park , Jung-Ho Do , Sang-Pil Sim , Jongshik Yoon , Kwanyoung Chun
发明人： Ho-Jun Kim , Chulhong Park , Jung-Ho Do , Sang-Pil Sim , Jongshik Yoon , Kwanyoung Chun
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/76895 , H01L21/823475 , H01L23/485 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes transistors provided on a substrate and including first dopant regions, first contacts extending from the first dopant regions in a first direction, a long via provided on the first contacts and connected in common to first contacts that are adjacent one another, and a common conductive line provided on the long via and extending in a second direction crossing the first direction. The common conductive line electrically connects the first dopant regions to each other.
摘要翻译：半导体器件包括设置在衬底上并包括第一掺杂区的晶体管，从第一方向从第一掺杂区延伸的第一触点，设置在第一触点上的长通路，并且被共同连接到彼此相邻的第一触点，以及设置在长通孔上并沿与第一方向交叉的第二方向延伸的公共导线。公共导线将第一掺杂区彼此电连接。

7. 发明授权

US07397704B2 Flash memory device and program method thereof 失效
标题翻译：闪存装置及其编程方法
公开(公告)号：US07397704B2
公开(公告)日：2008-07-08
申请号：US11616322
申请日：2006-12-27
申请人： Sang-Pil Sim
发明人： Sang-Pil Sim
IPC分类号： G11C16/00
CPC分类号： G11C16/3404 , G11C16/3454 , G11C16/3459
摘要： A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state.
摘要翻译：将闪速存储装置中的多个存储单元从第一状态编程到第二状态的方法包括使用根据程序循环数的增加具有增加的级别的验证电压来验证多个存储单元; 以及使用具有根据所述程序循环编号的增加而减小的增量的程序电压对所述多个存储单元进行编程，其中所述验证和编程步骤构成程序循环，所述程序循环在等级验证电压达到第二状态的电压范围。

8. 发明授权

US07271436B2 Flash memory devices including a pass transistor 有权
标题翻译：包括传输晶体管的闪存器件
公开(公告)号：US07271436B2
公开(公告)日：2007-09-18
申请号：US11021232
申请日：2004-12-23
申请人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
发明人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.
摘要翻译：闪存集成电路器件包括集成电路基板。集成电路基板上的单元阵列包括多个单元晶体管。位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。一个或多个第二传输晶体管耦合到第一传输晶体管。第二传输晶体管具有第二扩散结构。第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

9. 发明授权

US09536881B2 Semiconductor devices having fin shaped channels 有权
标题翻译：具有鳍形通道的半导体器件
公开(公告)号：US09536881B2
公开(公告)日：2017-01-03
申请号：US14259912
申请日：2014-04-23
申请人： Shigenobu Maeda , Sung-Bong Kim , Chang-Wook Moon , Dong-Hun Lee , Hyung-Soon Jang , Sang-Pil Sim
发明人： Shigenobu Maeda , Sung-Bong Kim , Chang-Wook Moon , Dong-Hun Lee , Hyung-Soon Jang , Sang-Pil Sim
IPC分类号： H01L27/11 , H01L27/092 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L27/0207 , H01L27/1108
摘要： Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain.
摘要翻译：提供半导体器件。半导体器件包括第一鳍片; 与第一鳍相交的第一栅电极; 第一鳍片上的第一栅电极的相应侧上的第一升高源极和/或漏极; 以及与第一鳍相邻的第一场电介质膜。第一场介电膜包括在第一翅片的顶表面下方的第一部分和从第一部分突出并且与第一升高源和/或漏极接触的第一鳍片的顶表面突出的第二部分。

10. 发明授权

US08836046B2 Semiconductor devices including protruding insulation portions between active fins 有权
标题翻译：半导体器件包括活性鳍片之间的突出绝缘部分
公开(公告)号：US08836046B2
公开(公告)日：2014-09-16
申请号：US14021465
申请日：2013-09-09
申请人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
发明人： Shigenobu Maeda , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L27/088 , H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
摘要翻译：半导体器件可以包括场绝缘层，其包括在第一和第二正交方向上延伸的平面主表面和从主表面相对于第一和第二正交方向突出特定距离的突出部分。第一和第二多通道活性翅片可以在场绝缘层上延伸，并且可以通过突出部分彼此分离。导电层可以从突出部分的最上表面延伸到与第一和第二多通道活性鳍片之间的突出部分交叉。

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