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1. 发明授权

US4196228A Fabrication of high resistivity semiconductor resistors by ion implanatation 失效
标题翻译：通过离子注入制造高电阻半导体电阻
公开(公告)号：US4196228A
公开(公告)日：1980-04-01
申请号：US926626
申请日：1978-07-21
申请人： Ury Priel , Jerry D. Gray , Allen H. Frederick
发明人： Ury Priel , Jerry D. Gray , Allen H. Frederick
IPC分类号： H01L21/265 , H01L21/8246 , H01L27/07 , H01L27/102 , H01L29/8605 , H01L21/425 , H01L21/441
CPC分类号： H01L27/11206 , H01L21/26513 , H01L21/2652 , H01L27/0772 , H01L27/1026 , H01L29/8605
摘要： This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders of the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions. Also disclosed are PNP transistor devices (both vertical and lateral types) having P type emitter regions preferably made with a Boron implant. A P-channel MOS device is also disclosed where the P+ source and drain regions are shallow, implanted regions.
摘要翻译：本公开涉及一种低功率一次写入的只读半导体存储器（PROM或可编程只读存储器）阵列，其中位于字线解码器和驱动器中的半导体电阻器以及存储器的位线解码器和读出放大器阵列被制造成具有高电阻率，从而允许半导体阵列以低得多的功率工作。这种一次写入的只读半导体存储器阵列的高电阻率半导体电阻器使用离子注入步骤制造，优选地在制造用于位线和字线解码器的NPN晶体管结构的基极和发射极扩散处理步骤之间的存储器阵列。高电阻率离子注入电阻器区域优选是通过离子注入通过薄二氧化硅层形成的浅的硼注入区域。使用浅的硼注入的高电阻率区域公开了各种电阻器件。还公开了具有优选由硼植入物制成的P型发射极区域的PNP晶体管器件（垂直和横向类型）。还公开了P沟道MOS器件，其中P +源极和漏极区是浅的注入区。

2. 发明授权

US3962589A Inverter with minimum skew 失效
标题翻译：逆变器最小偏移
公开(公告)号：US3962589A
公开(公告)日：1976-06-08
申请号：US548189
申请日：1975-02-10
申请人： Ury Priel , Robert A. Anselmo
发明人： Ury Priel , Robert A. Anselmo
IPC分类号： H03K19/088 , H03K19/40
CPC分类号： H03K19/088
摘要： A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.
摘要翻译：一种双反相器电路，其中第一反相器电路包括一对分相晶体管，一对用于馈送第一反相器电路中的上拉晶体管的基极，另一个用于在第二反相器晶体管的基极中馈送第二逆变电路。该电路在第一反相器的操作和第二反相器的导通时间之间提供最小延迟时间，同时在两个反相器中还提供有源上拉电路，即上拉晶体管，以确保快速操作时间当馈入大电容负载时，两个逆变器特别理想。

3. 发明授权

US4519076A Memory core testing system 失效
标题翻译：内存核心测试系统
公开(公告)号：US4519076A
公开(公告)日：1985-05-21
申请号：US334699
申请日：1981-12-28
申请人： Ury Priel , Giora Yaron , Mark S. Ebel
发明人： Ury Priel , Giora Yaron , Mark S. Ebel
IPC分类号： G11C29/50 , G06F11/22
CPC分类号： G11C29/50004 , G11C29/50 , G06F2201/81 , G11C16/04
摘要： A means for testing the threshold voltage changes in a programmable and erasable floating gate memory cell by accessing directly and exclusively the cells in the core, and the amplifiers that sense the operation of the cells, so as to measure the relative currents therein as an indication of threshold voltage parameters.
摘要翻译：一种用于通过直接和唯一地访问核心中的单元以及感测单元的操作的放大器来测试可编程和可擦除的浮动栅极存储单元中的阈值电压变化的装置，以便测量其中的相对电流作为指示的阈值电压参数。

4. 发明授权

US4402067A Bidirectional dual port serially controlled programmable read-only memory 失效
标题翻译：双向双端口串行可编程只读存储器
公开(公告)号：US4402067A
公开(公告)日：1983-08-30
申请号：US880007
申请日：1978-02-21
申请人： William E. Moss , Shlomo Waser , Ury Priel
发明人： William E. Moss , Shlomo Waser , Ury Priel
IPC分类号： G11C8/16 , G11C17/12 , G11C13/00
CPC分类号： G11C8/16 , G11C17/12
摘要： A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port. Multiplexing means and register means interact with the control circuits to formulate the data transfers.
摘要翻译：双向串行可编程只读存储器具有串行输入/输出（I / O）端口和并行I / O端口。通过选择适当的控制输入，本发明可以接收串行地址或数据信息，并将数据输出到并行或串行I / O端口。以类似的方式，并行I / O端口的地址可以用于以串行或并行形式产生输出数据。通常，并行I / O端口将用于将数据传输到微处理器和从微处理器传输数据，而串行I / O端口将用于将数据传输到外部接口和从外部接口传输数据。通过适当利用控制电路和适当使用控制信号，可以从并行I / O端口或串行I / O端口的并行形式从双向PROM读取数据。此外，数据可能从串行I / O端口传输到并行I / O端口或从并行I / O端口传输到串行I / O端口。多路复用装置和寄存器装置与控制电路交互以制定数据传输。

5. 发明授权

US4152627A Low power write-once, read-only memory array 失效
标题翻译：低功耗一次写入只读存储器阵列
公开(公告)号：US4152627A
公开(公告)日：1979-05-01
申请号：US805534
申请日：1977-06-10
申请人： Ury Priel , Jerry D. Gray , Allen H. Frederick
发明人： Ury Priel , Jerry D. Gray , Allen H. Frederick
IPC分类号： G11C17/16 , H01L27/102 , G11C17/00 , G11C7/00
CPC分类号： H01L27/1026 , G11C17/16
摘要： This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders or the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions. Also disclosed are PNP transistor devices (both vertical and lateral types) having P type emitter regions preferably made with a boron implant. A P-channel MOS device is also disclosed where the P+ source and drain regions are shallow, implanted regions.
摘要翻译：本公开涉及一种低功率一次写入的只读半导体存储器（PROM或可编程只读存储器）阵列，其中位于字线解码器和驱动器中的半导体电阻器以及存储器的位线解码器和读出放大器阵列被制造成具有高电阻率，从而允许半导体阵列以低得多的功率工作。这种一次写入的只读半导体存储器阵列的高电阻率半导体电阻器使用离子注入步骤制造，优选地在制造用于位线和字线解码器的NPN晶体管结构的基极和发射极扩散处理步骤之间或存储器阵列。高电阻率离子注入电阻器区域优选是通过离子注入通过薄二氧化硅层形成的浅的硼注入区域。使用浅的硼注入的高电阻率区域公开了各种电阻器件。还公开了具有优选由硼注入物制成的P型发射极区域的PNP晶体管器件（垂直和横向类型）。还公开了P沟道MOS器件，其中P +源极和漏极区是浅的注入区。

6. 发明授权

US3980898A Sense amplifier with tri-state bus line capabilities 失效
标题翻译：具有三态总线线路功能的感应放大器
公开(公告)号：US3980898A
公开(公告)日：1976-09-14
申请号：US557597
申请日：1975-03-12
申请人： Ury Priel
发明人： Ury Priel
IPC分类号： H03K19/018 , H03K19/00 , H03K19/0175 , H03K19/082 , H03K19/20 , H03K19/08 , H03K5/08 , H03K19/38 , H03K19/40
CPC分类号： H03K19/0021 , H03K19/017581 , H03K19/0826
摘要： A novel sense amplifier circuit providing conversion of MOS input signals to TTL output signals with tri-state logic output at the output data bus, the input circuit of the sense amplifier providing current sensing and programmable input thresholds for economical construction and enhanced speed of operation of the sense amplifier. A novel tri-state operation is provided for the input section of the sense amplifier to provide either a clamped voltage at the input data bus line during MOS to TTL communication or a floating input when it is desired that MOS devices on the input data bus are to communicate.
摘要翻译：一种新颖的读出放大器电路，提供MOS输入信号到输出数据总线上具有三态逻辑输出的TTL输出信号的转换，读出放大器的输入电路提供电流检测和可编程输入阈值，用于经济建设和提高运行速度读出放大器。提供了一种新颖的三态操作，用于读出放大器的输入部分，以便在MOS到TTL通信期间在输入数据总线处提供钳位电压，或者当希望输入数据总线上的MOS器件为沟通。

7. 发明授权

US4477825A Electrically programmable and erasable memory cell 失效
标题翻译：电可编程和可擦除存储单元
公开(公告)号：US4477825A
公开(公告)日：1984-10-16
申请号：US334700
申请日：1981-12-28
申请人： Giora Yaron , Ying K. Shum , Ury Priel , Jayasimha S. Prasad , Mark S. Ebel
发明人： Giora Yaron , Ying K. Shum , Ury Priel , Jayasimha S. Prasad , Mark S. Ebel
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02 , H01L29/04 , H01L29/06
CPC分类号： H01L29/7883
摘要： An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.
摘要翻译：一种电可编程和可擦除的存储单元，其中电荷载体通过薄氧化物隧道区在衬底中的浮置栅极和漏极区域之间被隧穿，所述隧道区域的边界被限制在两个漏极区域和浮动栅极。使用双路径将栅极的隧道区域连接到栅极的存储单元区域。

8. 发明授权

US4063117A Circuit for increasing the output current in MOS transistors 失效
标题翻译：增加MOS晶体管输出电流的电路
公开(公告)号：US4063117A
公开(公告)日：1977-12-13
申请号：US757710
申请日：1977-01-07
申请人： Ronald C. Laugesen , Ury Priel
发明人： Ronald C. Laugesen , Ury Priel
IPC分类号： H03K17/06 , H03K17/12 , H03K17/04 , H03K17/28 , H03K17/60
CPC分类号： H03K17/06
摘要： In order to increase the output current of an MOS transistor, its gate is provided with a switched capacitor drive. A tri-state inverter is used to drive the output transistor gate from an input source. A pair of delay elements are cascaded to drive one input of a NOR gate, the other input of which is fed an undelayed signal. The NOR gate is used to switch a capacitor that is also coupled to the output transistor gate. The juncture between the delays is coupled to the control electrode of the tri-state inverter. During the first delay interval, the capacitor and the output transistor gate electrode are charged. Then after the second delay interval, which is shorter than the first, the capacitor is discharged into the output transistor gate electrode which is thereby driven substantially in excess of the conventional drive level.
摘要翻译：为了增加MOS晶体管的输出电流，其栅极设置有开关电容器驱动器。三态反相器用于从输入源驱动输出晶体管栅极。一对延迟元件级联以驱动或非门的一个输入，其另一个输入端被馈送未延迟的信号。 NOR门用于切换也耦合到输出晶体管栅极的电容器。延迟之间的时刻与三态逆变器的控制电极耦合。在第一延迟间隔期间，电容器和输出晶体管栅电极被充电。然后在比第一延迟间隔短的第二延迟间隔之后，电容器被放电到输出晶体管栅电极中，从而驱动基本上超过常规驱动电平。

9. 发明授权

US4442510A Semiconductor memory byte clear circuit 失效
标题翻译：半导体存储器字节清零电路
公开(公告)号：US4442510A
公开(公告)日：1984-04-10
申请号：US334698
申请日：1981-12-28
申请人： Ury Priel , Giora Yaron , Mark S. Ebel
发明人： Ury Priel , Giora Yaron , Mark S. Ebel
IPC分类号： G11C16/16 , G11C16/20 , G11C11/40
CPC分类号： G11C16/20 , G11C16/16
摘要： A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the selected byte are used to introduce a clearing signal that dominates the non-clearing condition.
摘要翻译：用于清除半导体电可更改存储器中的所选字节的电路，其中用于任何一列字节的接地线与其他列的接地线隔离，字节的所有输出被推向非清除状态，并且仅使用所选字节的输出用于引入支配不清除条件的清除信号。

10. 发明授权

US4329703A Lateral PNP transistor 失效
标题翻译：横向PNP晶体管
公开(公告)号：US4329703A
公开(公告)日：1982-05-11
申请号：US141321
申请日：1980-04-18
申请人： Ury Priel , Jerry D. Gray , Allen H. Frederick
发明人： Ury Priel , Jerry D. Gray , Allen H. Frederick
IPC分类号： G11C17/16 , H01L27/07 , H01L27/102 , H01L29/08 , H01L29/735 , H01L29/8605 , H01L29/72 , H01L29/78 , H01L27/02 , H01L27/04
CPC分类号： H01L29/0808 , G11C17/16 , H01L27/0772 , H01L27/1026 , H01L29/0847 , H01L29/735 , H01L29/8605
摘要： Shallow, boron implanted regions are formed by ion implanting. Disclosed is a PNP transistor device (lateral type) having a P type emitter region preferably made with a boron implant.
摘要翻译：通过离子注入形成浅的硼注入区域。公开了具有优选由硼注入物制成的P型发射极区域的PNP晶体管器件（横向型）。

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