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1. 发明申请

US20180131375A1 COMMUNICATION BETWEEN INTEGRATED CIRCUITS 审中-公开
公开(公告)号：US20180131375A1
公开(公告)日：2018-05-10
申请号：US15569722
申请日：2016-04-28
申请人： Nordic Semiconductor ASA
发明人： Vegard Endersen , Per-Carsten Skoglund , Steffen Wiken
IPC分类号： H03K19/00 , G06F13/42
CPC分类号： H03K19/0021 , G06F13/4282 , G06F13/4291 , H03K21/38
摘要： A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.

2. 发明申请

US20140266326A1 Method for Reducing Overdrive Need in MOS Switching and Logic Circuit 有权
标题翻译：降低MOS开关和逻辑电路过载需求的方法
公开(公告)号：US20140266326A1
公开(公告)日：2014-09-18
申请号：US13853305
申请日：2013-03-29
申请人： DIALOG SEMICONDUCTOR B.V.
发明人： Michele Ancis , Rahul Todi
IPC分类号： H03K3/012
CPC分类号： H03K19/0013 , H03K19/0021 , H03K19/0027 , H03K19/018521
摘要： The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.
摘要翻译：本公开涉及将开关或逻辑电路的信号范围降低到电源范围以下的方法和电路。电路可以具有一个或多个阶段。可以为每个阶段单独设置供应水平。这可以基于从阶段到阶段的供应范围中的进展和/或调制实现数字和模拟控制的放大器/衰减器。阶段链可以通过根据输入信号的性质设置供应进度来提供所需的功率增益。通过包括电压源的通用设备网络降低信号电平，该电压源提供独立于流过电流的电压。将信号幅度与直流偏置耦合可以使信号摆幅低于有源器件的阈值电压。

3. 发明申请

US20140035614A1 LOGIC CIRCUITS USING NEURISTORS 有权
标题翻译：使用神经质的逻辑电路
公开(公告)号：US20140035614A1
公开(公告)日：2014-02-06
申请号：US13563167
申请日：2012-07-31
申请人： Matthew D. Pickett
发明人： Matthew D. Pickett
IPC分类号： H03K17/16
CPC分类号： H03K19/0813 , G06N3/049 , G06N3/0635 , H03K19/0021
摘要： Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input.
摘要翻译：描述使用神经元的逻辑电路。在一个示例中，电路包括多个神经电阻，每个神经电阻响应于超阈值输入电压而产生输出电压尖峰。多个阻抗耦合所述多个神经元以形成至少一个输入和输出，所述输出基于所述至少一个输入处的至少一个输入电压的逻辑运算选择性地提供输出电压尖峰。

4. 发明授权

US09882563B2 Method for reducing overdrive need in MOS switching and logic circuit 有权
公开(公告)号：US09882563B2
公开(公告)日：2018-01-30
申请号：US13853305
申请日：2013-03-29
申请人： Dialog Semiconductor B.V.
发明人： Michele Ancis , Rahul Todi
IPC分类号： H03K19/013 , H03K19/00 , H03K19/0185
CPC分类号： H03K19/0013 , H03K19/0021 , H03K19/0027 , H03K19/018521
摘要： The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

5. 发明申请

US20100091662A1 Defect-tolerant demultiplexers based on threshold logic 有权
标题翻译：基于阈值逻辑的容错解复用器
公开(公告)号：US20100091662A1
公开(公告)日：2010-04-15
申请号：US12288035
申请日：2008-10-15
申请人： Ron M. Roth , Joseph Warren Robinett , Philip J. Kuekes , R. Stanley Williams
发明人： Ron M. Roth , Joseph Warren Robinett , Philip J. Kuekes , R. Stanley Williams
IPC分类号： H04J3/14
CPC分类号： H04J3/047 , H03K17/002 , H03K19/0021 , H03K19/003
摘要： Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.
摘要翻译：本发明的实施例包括采用阈值逻辑“TL”元素的采用或可以通过解复用器交叉开关建模的缺陷容许解复用器交叉开关。阈值逻辑元件提供了对于容错解复用器交叉开关的内部信号线上的信号变化的容限，并因此提供产生内部信号变化的缺陷的容限。

6. 发明申请

US20090167406A1 Read circuit, variable resistive element device, and imaging device 审中-公开
标题翻译：读电路，可变电阻元件器件和成像器件
公开(公告)号：US20090167406A1
公开(公告)日：2009-07-02
申请号：US12314434
申请日：2008-12-10
申请人： Tsutomu Endo
发明人： Tsutomu Endo
IPC分类号： G06G7/18
CPC分类号： H03K19/0021
摘要： A read circuit includes: an integration circuit section configured to perform an integral operation and whose input is connected to an integration node; and a bias circuit connected between a connection node to which a variable resistive element is connected and the integration node. The bias circuit includes: an integration transistor whose source and drain are respectively connected to the connection node and the integration node; an operational amplifier whose output is connected to a gate of the integration transistor, to whose first input a bias voltage is supplied, and whose second input is connected to the source of the integration transistor; and a current switching circuit configured to provide or shut off a first current path. The first current path is a current path through which a current flowing between the drain and source of the integration transistor flows without passing through the connection node.
摘要翻译：读电路包括：积分电路部，被配置为执行积分运算，其输入连接到积分节点; 以及连接在连接有可变电阻元件的连接节点与积分节点之间的偏置电路。偏置电路包括：源极和漏极分别连接到连接节点和集成节点的积分晶体管; 输出与积分晶体管的栅极连接的运算放大器，第一输入端提供偏置电压，其第二输入端连接到积分晶体管的源极; 以及电流切换电路，被配置为提供或切断第一电流路径。第一电流路径是电流路径，流过积分晶体管的漏极和源极之间的电流流经该电流，而不通过连接节点。

7. 发明授权

US5856750A Interface circuit having receiving side circuit for controlling logical threshold values 失效
标题翻译：接口电路具有用于控制逻辑门限值的接收侧电路
公开(公告)号：US5856750A
公开(公告)日：1999-01-05
申请号：US807696
申请日：1997-02-28
申请人： Yoichi Koseki
发明人： Yoichi Koseki
IPC分类号： H03K3/0233 , H03K5/08 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948 , H03K5/153
CPC分类号： H03K19/018585 , H03K19/0021 , H03K5/082
摘要： In an interface circuit having a transmitting side circuit, a receiving side circuit and a transmission path connecting the transmitting side circuit and the receiving side circuit in a transmission system for transmitting a predetermined signal between the transmitting and receiving sides, the receiving side circuit has a receiver circuit having threshold control section for independently controlling a logical threshold value corresponding to rise of a received transmitting signal from low level to high level and a logical threshold value corresponding to fall of the received transmitting signal from high level to low level, and a control circuit for controlling the logical threshold values of the receiver circuit through the threshold control section in response to a voltage change in the transmitting signal.
摘要翻译：在具有发送侧电路的接收电路，接收侧电路和连接发送侧电路和接收侧电路的传输系统中，用于在发送侧和接收侧之间发送预定信号的发送系统中，接收侧电路具有接收机电路具有用于独立地控制对应于从低电平到高电平的接收的发送信号的上升的逻辑阈值的阈值控制部分和对应于从高电平到低电平的所接收的发送信号的下降的逻辑阈值;以及控制电路，用于响应于发送信号中的电压变化，通过阈值控制部分控制接收机电路的逻辑门限值。

8. 发明授权

US09685954B2 Pure memristive logic gate 有权
公开(公告)号：US09685954B2
公开(公告)日：2017-06-20
申请号：US14641482
申请日：2015-03-09
申请人： Technion Research and Development Foundation LTD.
发明人： Shahar Kvatinsky , Dmitry Belousov , Slavik Liman , Nimrod Wald , Guy Satat
IPC分类号： H03K19/173 , H03K19/003 , H03K19/08 , H03K19/00
CPC分类号： H03K19/00346 , H03K19/0021 , H03K19/02 , H03K19/0813 , H03K19/177
摘要： According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

9. 发明授权

US09473137B2 Non-volatile boolean logic operation circuit and operation method thereof 有权
标题翻译：非易失性布尔逻辑运算电路及其运算方法
公开(公告)号：US09473137B2
公开(公告)日：2016-10-18
申请号：US14867030
申请日：2015-09-28
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yaxiong Zhou , Yi Li , Huajun Sun
IPC分类号： H03K19/00 , H03K19/20 , H03K19/08
CPC分类号： H03K19/0002 , H03K19/0021 , H03K19/0813 , H03K19/20
摘要： A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.
摘要翻译：一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。

10. 发明申请

US20160105178A1 METHODS AND APPARATUSES FOR MULTIPLE CONCURRENT SUB-THRESHOLD VOLTAGE DOMAINS FOR OPTIMAL POWER PER GIVEN PERFORMANCE 有权
标题翻译：用于多个次级电压电压域的方法和装置，以获得最佳性能
公开(公告)号：US20160105178A1
公开(公告)日：2016-04-14
申请号：US14510981
申请日：2014-10-09
申请人： Uzi Zangi , Neil Feldman
发明人： Uzi Zangi , Neil Feldman
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/0021 , H03K19/0013 , H03K19/1774
摘要： A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements.
摘要翻译：一种使用子阈值技术实现ASIC的方法和流程，针对给定的应用性能优化了电压和过程的选择。一个实施例还可以在单个位置和路由块内实现同时使用的多个电压域。基于定时路径要求，在放置时间的电池之间动态地改变电压域。

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