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1. 发明授权

US4477825A Electrically programmable and erasable memory cell 失效
标题翻译：电可编程和可擦除存储单元
公开(公告)号：US4477825A
公开(公告)日：1984-10-16
申请号：US334700
申请日：1981-12-28
申请人： Giora Yaron , Ying K. Shum , Ury Priel , Jayasimha S. Prasad , Mark S. Ebel
发明人： Giora Yaron , Ying K. Shum , Ury Priel , Jayasimha S. Prasad , Mark S. Ebel
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02 , H01L29/04 , H01L29/06
CPC分类号： H01L29/7883
摘要： An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.
摘要翻译：一种电可编程和可擦除的存储单元，其中电荷载体通过薄氧化物隧道区在衬底中的浮置栅极和漏极区域之间被隧穿，所述隧道区域的边界被限制在两个漏极区域和浮动栅极。使用双路径将栅极的隧道区域连接到栅极的存储单元区域。

2. 发明授权

US4519076A Memory core testing system 失效
标题翻译：内存核心测试系统
公开(公告)号：US4519076A
公开(公告)日：1985-05-21
申请号：US334699
申请日：1981-12-28
申请人： Ury Priel , Giora Yaron , Mark S. Ebel
发明人： Ury Priel , Giora Yaron , Mark S. Ebel
IPC分类号： G11C29/50 , G06F11/22
CPC分类号： G11C29/50004 , G11C29/50 , G06F2201/81 , G11C16/04
摘要： A means for testing the threshold voltage changes in a programmable and erasable floating gate memory cell by accessing directly and exclusively the cells in the core, and the amplifiers that sense the operation of the cells, so as to measure the relative currents therein as an indication of threshold voltage parameters.
摘要翻译：一种用于通过直接和唯一地访问核心中的单元以及感测单元的操作的放大器来测试可编程和可擦除的浮动栅极存储单元中的阈值电压变化的装置，以便测量其中的相对电流作为指示的阈值电压参数。

3. 发明授权

US4442510A Semiconductor memory byte clear circuit 失效
标题翻译：半导体存储器字节清零电路
公开(公告)号：US4442510A
公开(公告)日：1984-04-10
申请号：US334698
申请日：1981-12-28
申请人： Ury Priel , Giora Yaron , Mark S. Ebel
发明人： Ury Priel , Giora Yaron , Mark S. Ebel
IPC分类号： G11C16/16 , G11C16/20 , G11C11/40
CPC分类号： G11C16/20 , G11C16/16
摘要： A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the selected byte are used to introduce a clearing signal that dominates the non-clearing condition.
摘要翻译：用于清除半导体电可更改存储器中的所选字节的电路，其中用于任何一列字节的接地线与其他列的接地线隔离，字节的所有输出被推向非清除状态，并且仅使用所选字节的输出用于引入支配不清除条件的清除信号。

4. 发明授权

US4441172A Semiconductor memory core program control circuit 失效
标题翻译：半导体存储器核心程序控制电路
公开(公告)号：US4441172A
公开(公告)日：1984-04-03
申请号：US334697
申请日：1981-12-28
申请人： Mark S. Ebel
发明人： Mark S. Ebel
IPC分类号： G11C16/22 , G11C16/30 , G11C7/00
CPC分类号： G11C16/30 , G11C16/225
摘要： A circuit to restrain the rise time of a programming pulse generated in an electrically alterable read-only semiconductor memory in which excessively sudden changes in the pulse are capacitively coupled, through active devices that can be built on the chip, to a grounding switch device so as to periodically drain away the control signal used to create the pulse.
摘要翻译：抑制在电可更改的只读半导体存储器中产生的编程脉冲的上升时间的电路，其中脉冲的过度突然的变化通过可以内置在芯片上的有源器件电容耦合到接地开关器件，从而以便周期性地排出用于产生脉冲的控制信号。

5. 发明授权

US5046045A Method of storing data in a read only memory to enhance access time 失效
标题翻译：将数据存储在只读存储器中以增强访问时间的方法
公开(公告)号：US5046045A
公开(公告)日：1991-09-03
申请号：US495359
申请日：1990-03-16
申请人： Mark S. Ebel , Michael R. McCoy
发明人： Mark S. Ebel , Michael R. McCoy
IPC分类号： G11C7/10 , G11C17/12
CPC分类号： G11C7/1006 , G11C17/12
摘要： The access time in reading data from a read only memory is enhanced by selectively inverting data stored in the memory. Each storage location along a wordline is weighted according to the distance of the bit location from the wordline driver, and bits stored therein are weighted by the bit location weight. The total weights of bits stored along the wordline are summed and compared with the maximum possible sum of weighted bits. If the ratio exceeds a preselected value, all bits of the wordline are inverted. The wordlines of a memory are provided with flag bits to indicate whether or not data stored on the wordline has been inverted.
摘要翻译：通过选择性地反转存储在存储器中的数据来增强从只读存储器读取数据的访问时间。沿着字线的每个存储位置根据位位置与字线驱动器的距离进行加权，并且存储在其中的位由位位置权重加权。将沿着字线存储的位的总权重相加并与加权位的最大可能和进行比较。如果该比率超过预选值，则字线的所有位都被反转。存储器的字线被提供有标志位，以指示存储在字线上的数据是否已被反转。

6. 发明授权

US4445205A Semiconductor memory core programming circuit 失效
标题翻译：半导体存储器核心编程电路
公开(公告)号：US4445205A
公开(公告)日：1984-04-24
申请号：US334695
申请日：1981-12-28
申请人： Mark S. Ebel
发明人： Mark S. Ebel
IPC分类号： G11C16/12 , G11C7/00
CPC分类号： G11C16/12
摘要： A programming pulse generating circuit, suitable for use on an electrically alterable read-only semiconductor memory, that decouples from the high voltage supply when in a standby condition so as to not draw current from the supply. Alternative voltage supply connections are effected by depletion mode devices.
摘要翻译：一种编程脉冲发生电路，适用于电可更改的只读半导体存储器，在待机状态下与高电压电源分离，以便不从电源抽取电流。替代电压供应连接由耗尽模式设备实现。

7. 发明授权

US6160733A Low voltage and low power static random access memory (SRAM) 失效
标题翻译：低电压和低功耗静态随机存取存储器（SRAM）
公开(公告)号：US6160733A
公开(公告)日：2000-12-12
申请号：US920682
申请日：1997-08-29
申请人： Mark S. Ebel
发明人： Mark S. Ebel
IPC分类号： G11C7/22 , G11C8/18 , G11C11/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A static random access memory having a static random access memory cell array, row address buffers for receiving row address signals, and column address buffers for receiving column address signals. The static random access memory also includes a clock chain circuit connected to the row address buffers and column address buffers such as to be responsive to transitions in the row address signals and column address signals by generating clock signals for accessing the static random access memory cell array. A method for accessing a static random access memory comprising detecting a transition occurring in a row address signal for addressing a static random access memory cell array; generating a plurality of clock signals in response to the transition in the row address signal; and accessing the static random access memory cell array.
摘要翻译：具有静态随机存取存储单元阵列，用于接收行地址信号的行地址缓冲器和用于接收列地址信号的列地址缓冲器的静态随机存取存储器。静态随机存取存储器还包括连接到行地址缓冲器和列地址缓冲器的时钟链电路，以便通过产生用于访问静态随机存取存储单元阵列的时钟信号来响应行地址信号和列地址信号中的转变。一种用于访问静态随机存取存储器的方法，包括检测在行地址信号中发生的转换，用于寻址静态随机存取存储单元阵列; 响应于行地址信号中的转变而产生多个时钟信号; 并访问静态随机存取存储单元阵列。

8. 发明授权

US5841724A Voltage source and memory-voltage switch in a memory chip 失效
标题翻译：存储器芯片中的电压源和存储器 - 电压开关
公开(公告)号：US5841724A
公开(公告)日：1998-11-24
申请号：US873445
申请日：1997-06-12
申请人： Mark S. Ebel , Robert Shen
发明人： Mark S. Ebel , Robert Shen
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/143
摘要： A circuit for connecting a memory cell matrix to voltage sources includes a voltage sensor responsive to the voltage levels of a first voltage source and of a second voltage source by producing a sense signal, and a voltage source coupler connected between the memory cell matrix and the voltage sensor. When the first voltage source voltage level is greater than a predetermined threshold voltage level, the sense signal causes the voltage source coupler to drive the first voltage source voltage level into the memory cell matrix. When the first voltage source voltage level falls to the threshold voltage level, the sense signal also causes the voltage source coupler to drive the second voltage source voltage level into the memory cell matrix to sustain memory cell data.
摘要翻译：用于将存储单元矩阵连接到电压源的电路包括响应于第一电压源的电压电平和通过产生感测信号的第二电压源的电压电平的电压传感器，以及连接在存储单元矩阵和电压传感器当第一电压源电压电平大于预定阈值电压电平时，感测信号使电压源耦合器将第一电压源电压电平驱动到存储单元矩阵中。当第一电压源电压电平下降到阈值电压电平时，感测信号也使电压源耦合器将第二电压源电压电平驱动到存储单元矩阵中以维持存储单元数据。

9. 发明授权

US4663740A High speed eprom cell and array 失效
标题翻译：高速eprom电池和阵列
公开(公告)号：US4663740A
公开(公告)日：1987-05-05
申请号：US750261
申请日：1985-07-01
申请人： Mark S. Ebel
发明人： Mark S. Ebel
IPC分类号： G11C16/04 , H01L29/788 , G11C11/34
CPC分类号： H01L29/7881 , G11C16/0441
摘要： A high speed EPROM cell comprises two floating gate field effect transistors and one field effect transistor. One of the floating gate transistors is smaller than the other floating gate transistor and functions as a programming transistor in developing charge on the interconnected floating gates. The larger dimensions of the other floating gate transistor allows increased read current and operating speed. The field effect transistor connects the larger floating gate transistor to a read drain terminal. The cell is readily fabricated using two doped polycrystalline semiconductor lines and two metallization lines in accordance with conventional semiconductor processing techniques.
摘要翻译：高速EPROM单元包括两个浮栅场效应晶体管和一个场效应晶体管。一个浮栅晶体管比另一个浮栅晶体管小，并且在互连浮栅上形成电荷时用作编程晶体管。另一个浮栅晶体管的较大尺寸允许增加的读取电流和操作速度。场效应晶体管将较大的浮置栅极晶体管连接到读取漏极端子。根据常规的半导体处理技术，电池容易使用两个掺杂的多晶半导体线和两个金属化线制造。

10. 发明授权

US3938109A High speed ECL compatible MOS-Ram 失效
标题翻译：高速ECL兼容MOS-Ram
公开(公告)号：US3938109A
公开(公告)日：1976-02-10
申请号：US551001
申请日：1975-02-19
申请人： John Gionis , Mark S. Ebel , William M. Regitz
发明人： John Gionis , Mark S. Ebel , William M. Regitz
IPC分类号： G11C11/402 , G11C11/408 , G11C11/4096 , G11C7/06 , G11C8/00
CPC分类号： G11C11/4023 , G11C11/4082 , G11C11/4096
摘要： A metal-oxide-silicon (MOS), random-access memory (RAM) which is emitter-coupled logic (ECL) compatible and which does not require any high level clock inputs. The memory utilizes pseudo-static cells which are refreshed with an asynchronous charge-pump signal generated on the memory chip. Buffers utilize the ECL reference signal to assure ECL compatibility. The memory employs dynamic decoding in two separate levels of decoding.
摘要翻译：金属氧化物硅（MOS），随机存取存储器（RAM），其是发射极耦合逻辑（ECL）兼容的，并且不需要任何高电平时钟输入。存储器利用在存储器芯片上产生的异步电荷泵信号刷新的伪静态单元。缓冲器利用ECL参考信号来确保ECL兼容性。存储器在两个独立的解码级别中采用动态解码。

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