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1. 发明授权

US06771162B1 Active cell crosspoint switch 有权
标题翻译：活动细胞交叉点开关
公开(公告)号：US06771162B1
公开(公告)日：2004-08-03
申请号：US09687724
申请日：2000-10-12
申请人： William E. Moss
发明人： William E. Moss
IPC分类号： H03K1700
CPC分类号： H03K19/09429 , H03K17/002 , H03K17/693
摘要： A high-speed, low distortion N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals. The crosspoint switch includes a switch cell array having N rows and M columns of switch cells. Each of N input lines convey the input signal arriving at a separate one of the N input signals to each switch cell of a corresponding array row. Each of M output lines convey output signals generated by cells of a corresponding array column to a separate switch output terminal. Each switch cell contains a CMOS tristate buffer and a memory cell for storing data controlling whether the tristate buffer is active or inactive. When a tristate buffer is active, it buffers an input signal appearing on one of the input lines to generate an output signal on one of the output lines. When inactive, a tristate buffer refrains from generating an output signal in response to its input signal. Each tristate buffer is configured so that much of its capacitance is decoupled from its input line when it is inactive so that it has minimal effect of signal propagation rates on its input line.
摘要翻译：高速，低失真NxM交叉点开关选择性地将输入信号到达N个输入端中的任何一个到M个输出端中的一个或多个。交叉点开关包括具有开关单元的N行和M列的开关单元阵列。 N个输入线中的每个输入信号将到达N个输入信号中的单独一个的输入信号传送到相应阵列行的每个开关单元。 M个输出线中的每一个将相应阵列列的单元产生的输出信号传送到单独的开关输出端。每个开关单元包含CMOS三态缓冲器和用于存储控制三态缓冲器是活动还是非活动的数据的存储单元。当三态缓冲器有效时，缓冲一条输入线上出现的输入信号，以在其中一根输出线上产生一个输出信号。当不活动时，三态缓冲器避免响应其输入信号产生输出信号。每个三态缓冲器被配置为使得其大部分电容在其不活动时与其输入线解耦，使得其在其输入线上具有最小的信号传播速率的影响。

2. 发明授权

US06356111B1 Crosspoint switch array with broadcast and implied disconnect operating modes 有权
标题翻译：具有广播和隐含断开操作模式的交叉点开关阵列
公开(公告)号：US06356111B1
公开(公告)日：2002-03-12
申请号：US09735430
申请日：2000-12-12
申请人： William E. Moss
发明人： William E. Moss
IPC分类号： H01L2500
CPC分类号： H04Q3/521 , H03K17/002 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13305
摘要： A high-speed N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals through a switch cell array having N rows and M columns of switch cells, each for selectively providing a signal path between one input terminal and one output terminal. Each switch cell contains a first memory cell holding a data bit, a second memory cell holding a control bit, and a transistor for making or braking a signal path in response to the control bit. This switch cell architecture enables the crosspoint switch to operate in normal, implied disconnect and broadcast modes. In the normal mode a controller creates a routing pattern by writing data bits to the second memory cells and then signals all switch cells to transfer their data bits into the first memory cells. In the implied disconnect mode, when any cell of a column is signaled to make a path, all other cells along that column automatically break their paths. The broadcast mode allows the controller to quickly configure the array to broadcast a signal and then restore a previous routing pattern.
摘要翻译：高速NxM交叉点开关通过具有N行和M列的开关单元的开关单元阵列选择性地将到达N个输入端中的任一个的输入信号路由到M个输出端中的一个或多个，每个用于选择性地提供一个输入端子和一个输出端子。每个开关单元包含保持数据位的第一存储单元，保持控制位的第二存储单元和用于响应于控制位而制作或制动信号路径的晶体管。该交换机单元架构使得交叉点交换机能够以正常的隐含的断开和广播模式运行。在正常模式中，控制器通过将数据位写入第二存储器单元来创建路由模式，然后将所有交换单元信号传送到第一存储器单元中。在隐含的断开模式下，当任何一个单元格的信号通知路径时，沿该列的所有其他单元格会自动断开其路径。广播模式允许控制器快速配置阵列以广播信号，然后恢复先前的路由模式。

3. 发明授权

US4814646A Programmable logic array using emitter-coupled logic 失效
标题翻译：使用发射极耦合逻辑的可编程逻辑阵列
公开(公告)号：US4814646A
公开(公告)日：1989-03-21
申请号：US715141
申请日：1985-03-22
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： H03K19/173 , G06F7/00 , H03K19/00 , H03K19/018 , H03K19/177 , H03K19/086
CPC分类号： H03K19/0016 , H03K19/01806 , H03K19/17708
摘要： An ECL Programmable Logic Array (PLA) having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.

4. 发明授权

US4574367A Memory cell and array 失效
标题翻译：存储单元和数组
公开(公告)号：US4574367A
公开(公告)日：1986-03-04
申请号：US551736
申请日：1983-11-10
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： G11C11/414 , G06F5/08 , G11C11/411 , G11C11/40
CPC分类号： G06F5/08
摘要： A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.
摘要翻译：一种包括多个行和列的多个存储单元的跌落式存储器阵列，每个存储单元包括一对具有三个发射极的交叉耦合晶体管，一个集电极和一个基极。耦合到每个晶体管的两个发射极中的每一个的字线上的控制电位控制数据位从这种存储单元的一行到另一行的传输。

5. 发明授权

US4402067A Bidirectional dual port serially controlled programmable read-only memory 失效
标题翻译：双向双端口串行可编程只读存储器
公开(公告)号：US4402067A
公开(公告)日：1983-08-30
申请号：US880007
申请日：1978-02-21
申请人： William E. Moss , Shlomo Waser , Ury Priel
发明人： William E. Moss , Shlomo Waser , Ury Priel
IPC分类号： G11C8/16 , G11C17/12 , G11C13/00
CPC分类号： G11C8/16 , G11C17/12
摘要： A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port. Multiplexing means and register means interact with the control circuits to formulate the data transfers.
摘要翻译：双向串行可编程只读存储器具有串行输入/输出（I / O）端口和并行I / O端口。通过选择适当的控制输入，本发明可以接收串行地址或数据信息，并将数据输出到并行或串行I / O端口。以类似的方式，并行I / O端口的地址可以用于以串行或并行形式产生输出数据。通常，并行I / O端口将用于将数据传输到微处理器和从微处理器传输数据，而串行I / O端口将用于将数据传输到外部接口和从外部接口传输数据。通过适当利用控制电路和适当使用控制信号，可以从并行I / O端口或串行I / O端口的并行形式从双向PROM读取数据。此外，数据可能从串行I / O端口传输到并行I / O端口或从并行I / O端口传输到串行I / O端口。多路复用装置和寄存器装置与控制电路交互以制定数据传输。

6. 发明授权

US06816057B2 Segmented crosspoint switch array 失效
标题翻译：分段交叉点开关阵列
公开(公告)号：US06816057B2
公开(公告)日：2004-11-09
申请号：US09766010
申请日：2001-01-19
申请人： Robert Allen Olah , William E. Moss
发明人： Robert Allen Olah , William E. Moss
IPC分类号： H03K1700
CPC分类号： H04Q3/521 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13305 , H04Q2213/13322
摘要： A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.

7. 发明授权

US4779010A Monostable logic gate in a programmable logic array 失效
标题翻译：可编程逻辑阵列中的单稳态逻辑门
公开(公告)号：US4779010A
公开(公告)日：1988-10-18
申请号：US891514
申请日：1986-07-29
申请人： William E. Moss
发明人： William E. Moss
IPC分类号： H03K5/007 , H03K5/151 , H03K19/00 , H03K19/017 , H03K19/177 , H03K3/355
CPC分类号： H03K19/01721 , H03K19/0013 , H03K19/17708 , H03K5/007 , H03K5/1515
摘要： An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead to ground in response to the signal (IN1) on the first input lead and a second NMOS transistor (60) which couples the output lead to ground in response to the signal (IN2) on the second input lead. A buffer (76) having a high output impedance is coupled to the output lead and tends to maintain the output lead in a constant state. When the signal on the first input lead goes high, the first NMOS transistor turns off and a PMOS transistor (64) turns on, thereby coupling the output lead to a high voltage source for a predetermined time period. If the second NMOS transistor is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer maintains the output lead in the high state.

8. 发明授权

US4151609A First in first out (FIFO) memory 失效
标题翻译：先进先出（FIFO）存储器
公开(公告)号：US4151609A
公开(公告)日：1979-04-24
申请号：US840827
申请日：1977-10-11
申请人： William E. Moss
发明人： William E. Moss
IPC分类号： G06F5/08 , G11C19/28 , G11C13/00 , G11C21/00
CPC分类号： G06F5/08 , G11C19/28 , G11C19/287
摘要： This disclosure is directed to a First In First Out memory which comprises a register, an input control section, a register control section, and an output control section. The imput control section allows data to be entered into the First In First Out memory while the register control section shifts the data through the memory queing up at the locations closest to the output. The output control allows data to be taken out of the FIFO at a different rate than data is entered into the memory by the input control section. The register control section monitors the succeeding location and the previous location in the register to determine when data may be shifted in the register.
摘要翻译：本公开涉及包括寄存器，输入控制部分，寄存器控制部分和输出控制部分的先进先出存储器。输入控制部分允许将数据输入到先进先出存储器，而寄存器控制部分通过存储器在最接近输出的位置排队移动数据。输出控制允许以与输入控制部分输入到存储器的数据不同的速率从FIFO中取出数据。寄存器控制部分监视寄存器中的后续位置和先前位置，以确定数据何时可能在寄存器中移位。

9. 发明授权

US4947060A High speed complimentary output stage utilizing current steering transistors and a single current source 失效
标题翻译：高速互补输出级采用电流转向晶体管和单个电流源
公开(公告)号：US4947060A
公开(公告)日：1990-08-07
申请号：US325402
申请日：1989-03-17
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： H03K19/173 , G06F7/00 , H03K19/00 , H03K19/018 , H03K19/177
CPC分类号： H03K19/0016 , H03K19/01806 , H03K19/17708
摘要： A novel output stage is disclosed which includes first and second output transistors for providing complementary output signals at inverting and noninverting output terminals in response to receipt of an input signal, wherein the output stage includes a single source of current and a pair of current steering transistors which are controlled by circuit means coupled between the input terminal and the control terminals of the current steering transistors to turn on the one of the current steering transistors which is coupled to the one of the inverting and noninverting output terminals which is undergoing a high voltage to low voltage transition and to turn off the other of the current steering transistors in response to the change of state of the input signal received at an input terminal.
摘要翻译：公开了一种新颖的输出级，其包括第一和第二输出晶体管，用于响应于输入信号的接收而在反相和同相输出端提供互补输出信号，其中输出级包括单个电流源和一对电流转向晶体管其由耦合在当前转向晶体管的输入端子和控制端子之间的电路装置控制，以接通耦合到正在经历高电压的反相和同相输出端子之一的电流转向晶体管中的一个，低电压转换，并且响应于在输入端子处接收的输入信号的状态的改变而关闭另一个电流转向晶体管。

10. 发明授权

US4864165A ECL programmable logic array with direct testing means for verification of programmed state 失效
标题翻译： ECL可编程逻辑阵列，具有用于验证编程状态的直接测试手段
公开(公告)号：US4864165A
公开(公告)日：1989-09-05
申请号：US141239
申请日：1988-01-05
申请人： Barry A. Hoberman , William E. Moss
发明人： Barry A. Hoberman , William E. Moss
IPC分类号： H03K19/173 , G06F7/00 , H03K19/00 , H03K19/018 , H03K19/177
CPC分类号： H03K19/0016 , H03K19/01806 , H03K19/17708
摘要： A novel ECL Programmable Logic Array (PLA) is provided which operates as an ECL PLA, having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.
摘要翻译：提供了一种新型的ECL可编程逻辑阵列（PLA），其作为ECL PLA工作，具有ECL电压电平兼容的输入和输出引线，从而提供高速PLA。提供了一种独特的编程手段，使得ECL PLA可以使用TTL兼容的编程电压电平进行编程，例如由普通和便宜的现有技术TTL PLA编程器提供。在另一个实施例中，通过使用发射器功能逻辑的每个读出放大器的设计实现更高的速度，使得感测晶体管和负载对共源共栅放大器起作用。在另一个实施例中，通过利用用于下拉PLA阵列的行的开关电流源下拉装置来实现较低功率的PLA装置。在另一个实施例中，通过允许每对输出终端共享预定义的一组产品项来实现低功率和用户便利性。在本发明的另一个实施例中，每个输出端子能够对其输出极性进行编程，以便提供期望的乘积项或该乘积项的倒数。

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