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1. 发明申请

US20140077304A1 AIRGAP STRUCTURE AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：航空结构及其制造方法
公开(公告)号：US20140077304A1
公开(公告)日：2014-03-20
申请号：US13617643
申请日：2012-09-14
申请人： Yu-Fong Huang , Kun-Mou Chan , Tzung-Ting Han
发明人： Yu-Fong Huang , Kun-Mou Chan , Tzung-Ting Han
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L27/11521 , H01L21/764 , H01L21/7682 , H01L27/11524 , H01L27/11568
摘要： A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.
摘要翻译：一种用于制造栅极结构的工艺，所述栅极结构具有由空间网络限定的多个栅极。具有气隙的密集WL区域内的字线（WL）空间，密集WL外部的那些空间基本上没有空气隙。还提供了具有跨越多个栅极的硅化物层的栅极结构。

2. 发明授权

US08890254B2 Airgap structure and method of manufacturing thereof 有权
标题翻译：气隙结构及其制造方法
公开(公告)号：US08890254B2
公开(公告)日：2014-11-18
申请号：US13617643
申请日：2012-09-14
申请人： Yu-Fong Huang , Kun-Mou Chan , Tzung-Ting Han
发明人： Yu-Fong Huang , Kun-Mou Chan , Tzung-Ting Han
IPC分类号： H01L21/70 , H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11521 , H01L21/764 , H01L21/7682 , H01L27/11524 , H01L27/11568
摘要： A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.
摘要翻译：一种用于制造栅极结构的工艺，所述栅极结构具有由空间网络限定的多个栅极。具有气隙的密集WL区域内的字线（WL）空间，密集WL外部的那些空间基本上没有空气隙。还提供了具有跨越多个栅极的硅化物层的栅极结构。

3. 发明申请

US20120161222A1 METHOD FOR FILLING A PHYSICAL ISOLATION TRENCH AND INTEGRATING A VERTICAL CHANNEL ARRAY WITH A PERIPHERY CIRCUIT 有权
标题翻译：用于填充物理隔离层的方法和用外围电路整合垂直通道阵列
公开(公告)号：US20120161222A1
公开(公告)日：2012-06-28
申请号：US12977910
申请日：2010-12-23
申请人： Yu-Fong Huang , Tzung-Ting Han
发明人： Yu-Fong Huang , Tzung-Ting Han
IPC分类号： H01L29/772 , H01L21/762 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/76229 , H01L27/11573 , H01L27/11575 , H01L29/7827 , H01L29/7926
摘要： A method of processing a semiconductor structure may include preparing a vertical channel memory structure for filling of a physical isolation trench formed therein. The physical isolation trench may be formed between active structures adjacent to each other and extending in a first direction. The active structures may have channels adjacent to sides of the active structures that are opposite to sides of the active structures that are adjacent to the physical isolation trench. The method may further include filling the physical isolation trench in connection with application of a multi-dielectric layer (ex. an oxide-nitride-oxide (ONO) layer), a polysilicon liner and/or an oxide film. A corresponding apparatus and method for integrating such a structure with a planar periphery are also provided.
摘要翻译：处理半导体结构的方法可以包括制备用于填充其中形成的物理隔离沟槽的垂直沟道存储器结构。物理隔离沟槽可以形成在彼此相邻并在第一方向上延伸的有源结构之间。活性结构可以具有与活性结构的与物理隔离沟槽相邻的与活性结构的侧面相对的相邻的通道。该方法可以进一步包括与施加多电介质层（例如氧化物 - 氮化物 - 氧化物（ONO）层），多晶硅衬垫和/或氧化物膜相结合地填充物理隔离沟槽。还提供了一种用于将这种结构与平面周边集成的相应装置和方法。

4. 发明申请

US20120119282A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路装置及制造半导体集成电路装置的方法
公开(公告)号：US20120119282A1
公开(公告)日：2012-05-17
申请号：US12945659
申请日：2010-11-12
申请人： Yu-Fong Huang , Tzung-Ting Han , Wen-Pin Lu
发明人： Yu-Fong Huang , Tzung-Ting Han , Wen-Pin Lu
IPC分类号： H01L27/11 , H01L21/336
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/11582
摘要： A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.
摘要翻译：用于半导体集成电路器件的系统，方法和布局允许改进可以包括触点和其它金属互连结构的各种后端结构的缩小。所得到的结构可以包括半导体衬底，形成在半导体衬底上的掩埋扩散区，以及硅化物膜，例如硅化钨（WSix）和自对准硅化物（自对准硅）膜中的至少一种，例如钴硅化物（CoSi）和/或硅化镍（NiSi），在掩埋扩散（BD）层之上。半导体集成电路还可以包括形成在接触层的至少一部分上的存储器栅极结构。

5. 发明授权

US08916920B2 Memory structure with planar upper surface 有权
标题翻译：具有平面上表面的记忆结构
公开(公告)号：US08916920B2
公开(公告)日：2014-12-23
申请号：US13186095
申请日：2011-07-19
申请人： Yu-Fong Huang , Tzung-Ting Han
发明人： Yu-Fong Huang , Tzung-Ting Han
IPC分类号： H01L29/76 , H01L27/115
CPC分类号： H01L27/11531 , H01L27/11548
摘要： A memory structure having a memory cell region and a non-memory cell region is provided. The memory structure includes a plurality of memory cells and a conductive material. The plurality of memory cells are disposed in the memory cell region, wherein a plurality of first concave portions are present in the plurality of memory cells. The conductive material extends across the memory cell region and the non-memory cell region, covers the plurality of memory cells, and extends into the plurality of first concave portions.
摘要翻译：提供了具有存储单元区域和非存储单元区域的存储器结构。存储器结构包括多个存储单元和导电材料。多个存储单元设置在存储单元区域中，其中多个第一凹部存在于多个存储单元中。导电材料延伸穿过存储单元区域和非存储单元区域，覆盖多个存储单元，并延伸到多个第一凹入部分中。

6. 发明授权

US08466064B2 Semiconductor integrated circuit device and method of manufacturing a semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US08466064B2
公开(公告)日：2013-06-18
申请号：US12945659
申请日：2010-11-12
申请人： Yu-Fong Huang , Tzung-Ting Han , Wen-Pin Lu
发明人： Yu-Fong Huang , Tzung-Ting Han , Wen-Pin Lu
IPC分类号： H01L21/44
CPC分类号： H01L29/7926 , H01L27/11565 , H01L27/11582
摘要： A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.
摘要翻译：用于半导体集成电路器件的系统，方法和布局允许改进可以包括触点和其它金属互连结构的各种后端结构的缩小。所得到的结构可以包括半导体衬底，形成在半导体衬底上的掩埋扩散区，以及硅化物膜，例如硅化钨（WSix）和自对准硅化物（自对准硅）膜中的至少一种，例如钴硅化物（CoSi）和/或硅化镍（NiSi），在掩埋扩散（BD）层之上。半导体集成电路还可以包括形成在接触层的至少一部分上的存储器栅极结构。

7. 发明授权

US08623726B2 Method for filling a physical isolation trench and integrating a vertical channel array with a periphery circuit 有权
标题翻译：用于填充物理隔离沟槽并将垂直沟道阵列与外围电路集成的方法
公开(公告)号：US08623726B2
公开(公告)日：2014-01-07
申请号：US12977910
申请日：2010-12-23
申请人： Yu-Fong Huang , Tzung-Ting Han
发明人： Yu-Fong Huang , Tzung-Ting Han
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/76229 , H01L27/11573 , H01L27/11575 , H01L29/7827 , H01L29/7926
摘要： A method of processing a semiconductor structure may include preparing a vertical channel memory structure for filling of a physical isolation trench formed therein. The physical isolation trench may be formed between active structures adjacent to each other and extending in a first direction. The active structures may have channels adjacent to sides of the active structures that are opposite to sides of the active structures that are adjacent to the physical isolation trench. The method may further include filling the physical isolation trench in connection with application of a multi-dielectric layer (ex. an oxide-nitride-oxide (ONO) layer), a polysilicon liner and/or an oxide film. A corresponding apparatus and method for integrating such a structure with a planar periphery are also provided.
摘要翻译：处理半导体结构的方法可以包括制备用于填充其中形成的物理隔离沟槽的垂直沟道存储器结构。物理隔离沟槽可以形成在彼此相邻并在第一方向上延伸的有源结构之间。活性结构可以具有与活性结构的与物理隔离沟槽相邻的与活性结构的侧面相对的相邻的通道。该方法可以进一步包括与应用多电介质层（例如氧化物 - 氮化物 - 氧化物（ONO）层），多晶硅衬垫和/或氧化物膜相结合地填充物理隔离沟槽。还提供了一种用于将这种结构与平面周边集成的相应装置和方法。

8. 发明申请

US20130020624A1 MEMORY STRUCTURE 有权
标题翻译：内存结构
公开(公告)号：US20130020624A1
公开(公告)日：2013-01-24
申请号：US13186095
申请日：2011-07-19
申请人： Yu-Fong Huang , Tzung-Ting Han
发明人： Yu-Fong Huang , Tzung-Ting Han
IPC分类号： H01L29/788
CPC分类号： H01L27/11531 , H01L27/11548
摘要： A memory structure having a memory cell region and a non-memory cell region is provided. The memory structure includes a plurality of memory cells and a conductive material. The plurality of memory cells are disposed in the memory cell region, wherein a plurality of first concave portions are present in the plurality of memory cells. The conductive material extends across the memory cell region and the non-memory cell region, covers the plurality of memory cells, and extends into the plurality of first concave portions.
摘要翻译：提供了具有存储单元区域和非存储单元区域的存储器结构。存储器结构包括多个存储单元和导电材料。多个存储单元设置在存储单元区域中，其中多个第一凹部存在于多个存储单元中。导电材料延伸穿过存储单元区域和非存储单元区域，覆盖多个存储单元，并延伸到多个第一凹入部分中。

9. 发明授权

US08779500B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08779500B2
公开(公告)日：2014-07-15
申请号：US12691964
申请日：2010-01-22
申请人： Yu-Fong Huang , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
发明人： Yu-Fong Huang , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7926
摘要： A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.
摘要翻译：提供了一种存储器件，包括衬底，导电层，电荷存储层，多个隔离结构，多个第一掺杂区和多个第二掺杂区。衬底具有多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。隔离结构分别设置在两个相邻沟槽之间的衬底中。第一掺杂区域分别设置在每个隔离结构和每个沟槽之间的衬底的上部。第二掺杂区域设置在沟槽的底部下方的衬底中，其中每个隔离结构设置在两个相邻的第二掺杂区域之间。

10. 发明授权

US08391063B2 Method of operating memory cell 有权
标题翻译：操作存储单元的方法
公开(公告)号：US08391063B2
公开(公告)日：2013-03-05
申请号：US12835075
申请日：2010-07-13
申请人： Yu-Fong Huang , Teng-Hao Yeh , Miao-Chih Hsu , Tzung-Ting Han
发明人： Yu-Fong Huang , Teng-Hao Yeh , Miao-Chih Hsu , Tzung-Ting Han
IPC分类号： G11C11/34
CPC分类号： H01L29/7923 , G11C11/5621 , G11C16/0458 , H01L29/66833
摘要： A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively.
摘要翻译：提供了一种操作存储单元的方法。存储单元在基板和字线之间的电荷存储层中具有第一，第二，第三和第四存储区域。第一和第二存储区分别与衬底的突出部分的一侧的下部和上部相邻，并且第三和第四存储区分别在其另一侧的下部和上部相邻。第二和第三存储区域被认为是顶部存储区域。当顶部存储区域被编程时，第一正电压被施加到字线，第二正电压被施加到突出部分的顶部中的顶位线，并且底电压被施加到第一和第二底部位于突出部分旁边的基板中的位线。

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