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1. 发明授权

US08836004B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08836004B2
公开(公告)日：2014-09-16
申请号：US12724053
申请日：2010-03-15
申请人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
发明人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
IPC分类号： H01L29/76 , H01L27/115 , H01L29/792
CPC分类号： H01L29/792 , H01L27/11568
摘要： A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.
摘要翻译：提供了包括基板，导电层，电荷存储层，第一和第二掺杂剂区以及第一和第二单元掺杂区的存储器件。多个沟槽部署在基板中。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。具有第一导电类型的第一和第二掺杂剂区域分别在沟槽的底部和衬底的上部分别配置在基板的两个相邻的沟槽之间。具有第二导电类型的第一和第二电池掺杂剂区域分别配置在沟槽的侧表面的下部和与第二掺杂剂区的底部相邻的衬底中的衬底中。第一和第二导电类型是不同的掺杂剂类型。

2. 发明授权

US08779500B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08779500B2
公开(公告)日：2014-07-15
申请号：US12691964
申请日：2010-01-22
申请人： Yu-Fong Huang , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
发明人： Yu-Fong Huang , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7926
摘要： A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.
摘要翻译：提供了一种存储器件，包括衬底，导电层，电荷存储层，多个隔离结构，多个第一掺杂区和多个第二掺杂区。衬底具有多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。隔离结构分别设置在两个相邻沟槽之间的衬底中。第一掺杂区域分别设置在每个隔离结构和每个沟槽之间的衬底的上部。第二掺杂区域设置在沟槽的底部下方的衬底中，其中每个隔离结构设置在两个相邻的第二掺杂区域之间。

3. 发明授权

US08391063B2 Method of operating memory cell 有权
标题翻译：操作存储单元的方法
公开(公告)号：US08391063B2
公开(公告)日：2013-03-05
申请号：US12835075
申请日：2010-07-13
申请人： Yu-Fong Huang , Teng-Hao Yeh , Miao-Chih Hsu , Tzung-Ting Han
发明人： Yu-Fong Huang , Teng-Hao Yeh , Miao-Chih Hsu , Tzung-Ting Han
IPC分类号： G11C11/34
CPC分类号： H01L29/7923 , G11C11/5621 , G11C16/0458 , H01L29/66833
摘要： A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively.
摘要翻译：提供了一种操作存储单元的方法。存储单元在基板和字线之间的电荷存储层中具有第一，第二，第三和第四存储区域。第一和第二存储区分别与衬底的突出部分的一侧的下部和上部相邻，并且第三和第四存储区分别在其另一侧的下部和上部相邻。第二和第三存储区域被认为是顶部存储区域。当顶部存储区域被编程时，第一正电压被施加到字线，第二正电压被施加到突出部分的顶部中的顶位线，并且底电压被施加到第一和第二底部位于突出部分旁边的基板中的位线。

4. 发明申请

US20110255350A1 METHOD OF OPERATING MEMORY CELL 有权
标题翻译：操作记忆体的方法
公开(公告)号：US20110255350A1
公开(公告)日：2011-10-20
申请号：US12835075
申请日：2010-07-13
申请人： Yu-Fon Huang , Teng-Hao Yeh , Miao-Chih Hsu , Tzung-Ting Han
发明人： Yu-Fon Huang , Teng-Hao Yeh , Miao-Chih Hsu , Tzung-Ting Han
IPC分类号： G11C16/04
CPC分类号： H01L29/7923 , G11C11/5621 , G11C16/0458 , H01L29/66833
摘要： A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively.
摘要翻译：提供了一种操作存储单元的方法。存储单元在基板和字线之间的电荷存储层中具有第一，第二，第三和第四存储区域。第一和第二存储区分别与衬底的突出部分的一侧的下部和上部相邻，并且第三和第四存储区分别在其另一侧的下部和上部相邻。第二和第三存储区域被认为是顶部存储区域。当顶部存储区域被编程时，第一正电压被施加到字线，第二正电压被施加到突出部分的顶部中的顶位线，并且底电压被施加到第一和第二底部位于突出部分旁边的基板中的位线。

5. 发明申请

US20110180864A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110180864A1
公开(公告)日：2011-07-28
申请号：US12691964
申请日：2010-01-22
申请人： YU-FONG HUANG , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
发明人： YU-FONG HUANG , Miao-Chih Hsu , Kuan-Fu Chen , Tzung-Ting Han
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7926
摘要： A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.
摘要翻译：提供了一种存储器件，包括衬底，导电层，电荷存储层，多个隔离结构，多个第一掺杂区和多个第二掺杂区。衬底具有多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。隔离结构分别设置在两个相邻沟槽之间的衬底中。第一掺杂区域分别设置在每个隔离结构和每个沟槽之间的衬底的上部。第二掺杂区域设置在沟槽的底部下方的衬底中，其中每个隔离结构设置在两个相邻的第二掺杂区域之间。

6. 发明申请

US20080026561A1 METHODS OF TRENCH AND CONTACT FORMATION IN MEMORY CELLS 有权
标题翻译：记忆细胞中TRENCH和接触形成的方法
公开(公告)号：US20080026561A1
公开(公告)日：2008-01-31
申请号：US11459990
申请日：2006-07-26
申请人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
发明人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.
摘要翻译：使用这种方法形成的接触形成方法和存储器阵列，该方法包括提供存储阵列，该存储阵列具有设置在半导体衬底的表面下方的多个位线，以及设置在衬底的表面上方且横向于衬底的多个字线位线在所述多个字线上形成硬掩模材料层，其中在所述硬掩模材料层中的开口下方暴露位于所述位线中的至少一个之上并且在两个连续字线之间的区域; 在硬掩模材料层上形成绝缘材料层; 在所述区域上方的绝缘材料层中形成连续的沟槽和通孔图案，使得所述至少一个位线的一部分暴露在所述图案下方; 以及形成互连，其包括设置在所述连续沟槽中的导电材料和通孔图案，其中所述互连与所述至少一个位线的所述暴露部分导电接触。

7. 发明授权

US07666784B2 Methods of trench and contact formation in memory cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US07666784B2
公开(公告)日：2010-02-23
申请号：US12211603
申请日：2008-09-16
申请人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
发明人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.
摘要翻译：使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

8. 发明授权

US07435648B2 Methods of trench and contact formation in memory cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US07435648B2
公开(公告)日：2008-10-14
申请号：US11459990
申请日：2006-07-26
申请人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
发明人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.
摘要翻译：使用这种方法形成的接触形成方法和存储器阵列，该方法包括提供存储阵列，该存储阵列具有设置在半导体衬底的表面下方的多个位线，以及设置在衬底的表面上方且横向于衬底的多个字线位线在所述多个字线上形成硬掩模材料层，其中在所述硬掩模材料层中的开口下方暴露位于所述位线中的至少一个之上并且在两个连续字线之间的区域; 在硬掩模材料层上形成绝缘材料层; 在所述区域上方的绝缘材料层中形成连续的沟槽和通孔图案，使得所述至少一个位线的一部分暴露在所述图案下方; 以及形成互连，其包括设置在所述连续沟槽中的导电材料和通孔图案，其中所述互连与所述至少一个位线的所述暴露部分导电接触。

9. 发明申请

US20110220986A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110220986A1
公开(公告)日：2011-09-15
申请号：US12724053
申请日：2010-03-15
申请人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
发明人： Yu-Fong Huang , I-Shen Tsai , Shang-Wei Lin , Miao-Chih Hsu , Kuan-Fu Chen
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11568
摘要： A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.
摘要翻译：提供了包括基板，导电层，电荷存储层，第一和第二掺杂剂区以及第一和第二单元掺杂区的存储器件。多个沟槽部署在基板中。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。具有第一导电类型的第一和第二掺杂剂区域分别在沟槽的底部和衬底的上部分别配置在衬底中。具有第二导电类型的第一和第二单元掺杂区域分别配置在沟槽的侧表面的下部和与第二掺杂区的底部相邻的衬底中的衬底中。第一和第二导电类型是不同的掺杂剂类型。

10. 发明申请

US20090011594A1 Methods of Trench and Contact Formation in Memory Cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US20090011594A1
公开(公告)日：2009-01-08
申请号：US12211603
申请日：2008-09-16
申请人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
发明人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： H01L21/768
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.
摘要翻译：使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

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