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1. 发明授权

US06347344B1 Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor 有权
标题翻译：集成多媒体系统与本地处理器，数据传输交换机，处理模块，固定功能单元，数据流，接口单元和多路复用器，均集成在多媒体处理器
公开(公告)号：US06347344B1
公开(公告)日：2002-02-12
申请号：US09172286
申请日：1998-10-14
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F300
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A multiplexer is coupled to the interface unit and provides access between a selected number of I/O device driver units and external I/O devices via output pins. A plurality of external I/O devices are coupled to the multimedia processor.
摘要翻译：集成多媒体系统具有设置在集成电路中的多媒体处理器。该系统包括耦合到多媒体处理器的第一主机处理器系统。第二本地处理器被布置在控制多媒体处理器的操作的多媒体处理器内。数据传输开关设置在多媒体处理器内并且耦合到第二处理器，该第二处理器将数据传送到多媒体处理器的各个模块。固定功能单元设置在所述多媒体处理器内，耦合到所述第二处理器和所述数据传输开关，并且被配置为执行三维图形操作。数据流器耦合到所述数据传输开关，并且被配置为调度在多个模块根据相应的信道分配设置在多媒体处理器内。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多路复用器耦合到接口单元，并通过输出引脚提供所选数量的I / O设备驱动单元和外部I / O设备之间的访问。多个外部I / O设备耦合到多媒体处理器。

2. 发明授权

US5898677A Integrated circuit device having a switched routing network 失效
标题翻译：具有交换路由网络的集成电路设备
公开(公告)号：US5898677A
公开(公告)日：1999-04-27
申请号：US782585
申请日：1997-01-13
申请人： Richard Deeley , Carlos Dangelo
发明人： Richard Deeley , Carlos Dangelo
IPC分类号： G06F17/50 , H03K19/173 , H04J3/04 , H04Q11/04 , H01L29/00
CPC分类号： H04Q11/0421 , G06F17/5045 , H03K19/1737 , H04J3/047
摘要： Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area. One aspect of the invention is directed to using auto-routing switching techniques for combining signals. Another aspect is directed to applying these combining/expanding techniques to the integrated circuit design process.
摘要翻译：通过提高集成电路中信号线路的信息效率，可以提高集成电路设计中的信号区域效率。根据行程长度，旅行路径和信息内容对信号进行优先排序，选择候选信号进行组合。具有低信息含量和端点之间距离更大的信号使固定布线的利用率降低，并提供最佳的改进选择。通过集成电路从点到点行进相似（基本上平行）路径的候选信号被组合以提高芯片面积利用效率。描述了将低信息内容信号组合到少数电线上的各种技术，通过少量电线传输它们，并在其目的地重新扩展它们。假设组合/扩展电路占用的空间比原来要求的点对点布线少，则芯片面积的净减少。本发明的一个方面涉及使用自动路由切换技术来组合信号。另一方面涉及将这些组合/扩展技术应用于集成电路设计过程。

3. 发明授权

US5638288A Separable cells having wiring channels for routing signals between surrounding cells 失效
标题翻译：可分离的单元具有用于在周围单元之间路由信号的布线通道
公开(公告)号：US5638288A
公开(公告)日：1997-06-10
申请号：US295094
申请日：1994-08-24
申请人： Richard Deeley
发明人： Richard Deeley
IPC分类号： G06F17/50 , H01L27/02 , H01L27/118 , H01L21/02
CPC分类号： H01L27/0207 , G06F17/5072 , H01L27/118
摘要： On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e.g., timing constraints) will be met. A plurality of surrounding cells may be interconnected by routing their signals in stacked wiring layers. The megacell may be split or stretched about two or more parting lines to create two or more wiring channels.
摘要翻译：在采用大的预定义电路块的集成电路设计中，通过允许在大电路块（megacell）之间的周围（例如，在相对的两侧）的电路块之间的信号物理地通过兆位来提高芯片面积利用率和信号路由。大型电力设备布置成使得通过电力分配器定义“分流线”。巨型电路内的电路布置成使得电路“跨越”分离线。然后可以围绕分型线分离或拉伸巨型电位器，以产生布线通道。布线通道用于从周围的单元（电路块）通过大电路块（megacell）路由信号。在分开线的相对侧上的拉伸或分裂的电池的分离部分之间的信号可以路由在一个金属层中，而通过电池的周围电池的连接可以在另一个金属层中布线。定义了最大分割或拉伸距离，对于该最大分割或拉伸距离将满足巨型飞机性能规格（例如，时间约束）。可以通过在堆叠的布线层中布置它们的信号来互连多个周围的单元。大型电池可以分开或拉伸约两个或更多个分型线以产生两个或更多个布线通道。

4. 发明授权

US07457890B2 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US07457890B2
公开(公告)日：2008-11-25
申请号：US11589695
申请日：2006-10-30
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F3/00 , G06F15/76 , G06F1/00 , G06F15/16 , G06F13/14
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.
摘要翻译：具有多媒体处理器的集成多媒体系统被布置在具有耦合到多媒体处理器的第一主处理器系统的集成电路中，以及设置在多媒体处理器内的用于控制多媒体处理器的操作的第二本地处理器。数据传输开关耦合到第二处理器，用于将数据传送到处理器的各个模块，其中至少一个是数据高速缓存。数据传输交换机在缓存和处理器内的模块之间的任一方向上传输数据。数据流器根据相应的信道分配来调度在多媒体处理器内布置的各个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多个外部I / O设备经由多路复用器耦合到多个I / O设备驱动器单元。

5. 发明授权

US5905655A Separable cells having wiring channels for routing signals between surrounding cells 失效
标题翻译：可分离的单元具有用于在周围单元之间路由信号的布线通道
公开(公告)号：US5905655A
公开(公告)日：1999-05-18
申请号：US871212
申请日：1997-06-09
申请人： Richard Deeley
发明人： Richard Deeley
IPC分类号： G06F17/50 , H01L27/02 , H01L27/118
CPC分类号： H01L27/0207 , G06F17/5072 , H01L27/118
摘要： On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e.g., timing constraints) will be met. A plurality of surrounding cells may be interconnected by routing their signals in stacked wiring layers. The megacell may be split or stretched about two or more parting lines to create two or more wiring channels.
摘要翻译：在采用大的预定义电路块的集成电路设计中，通过允许在大电路块（megacell）之间的周围（例如，在相对的两侧）的电路块之间的信号物理地通过兆位来提高芯片面积利用率和信号路由。大型电力设备布置成使得通过电力分配器定义“分流线”。巨型电路内的电路布置成使得电路“跨越”分离线。然后可以围绕分型线分离或拉伸巨型电位器，以产生布线通道。布线通道用于从周围的单元（电路块）通过大电路块（megacell）路由信号。在分开线的相对侧上的拉伸或分裂的电池的分离部分之间的信号可以路由在一个金属层中，而通过电池的周围电池的连接可以在另一个金属层中布线。定义了最大分割或拉伸距离，对于该最大分割或拉伸距离将满足巨型飞机性能规格（例如，时间约束）。可以通过在堆叠的布线层中布置它们的信号来互连多个周围的单元。大型电池可以分开或拉伸约两个或更多个分型线以产生两个或更多个布线通道。

6. 发明授权

US5615126A High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing 失效
标题翻译：用于通过复用减少信号线数量的集成电路的高速内部互连技术
公开(公告)号：US5615126A
公开(公告)日：1997-03-25
申请号：US294973
申请日：1994-08-24
申请人： Richard Deeley , Carlos Dangelo
发明人： Richard Deeley , Carlos Dangelo
IPC分类号： G06F17/50 , H03K19/173 , H04J3/04 , H04Q11/04 , H02B1/20
CPC分类号： H04Q11/0421 , G06F17/5045 , H03K19/1737 , H04J3/047
摘要： Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area. One aspect of the invention is directed to using auto-routing switching techniques for combining signals. Another aspect is directed to applying these combining/expanding techniques to the integrated circuit design process.
摘要翻译：通过提高集成电路中信号线路的信息效率，可以提高集成电路设计中的信号区域效率。通过根据行程长度，旅行路径和信息内容对信号进行优先排序，选择候选信号进行组合。具有低信息含量和端点之间距离更大的信号使固定布线的利用率降低，并提供最佳的改进选择。通过集成电路从点到点行进相似（基本上平行）路径的候选信号被组合以提高芯片面积利用效率。描述了将低信息内容信号组合到少数电线上的各种技术，通过少量电线传输它们，并在其目的地重新扩展它们。假设组合/扩展电路占用的空间比原来要求的点对点布线少，则芯片面积的净减少。本发明的一个方面涉及使用自动路由切换技术来组合信号。另一方面涉及将这些组合/扩展技术应用于集成电路设计过程。

7. 发明授权

US07272670B2 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US07272670B2
公开(公告)日：2007-09-18
申请号：US09777003
申请日：2001-02-05
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F3/00 , G06F15/76 , G06F1/00 , G06F15/16 , G06F13/14
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.
摘要翻译：集成多媒体系统具有设置在集成电路中的多媒体处理器。处理器被布置在控制多媒体处理器的操作的多媒体处理器内。数据传输交换机设置在多媒体处理器内并且耦合到处理器，该处理器将数据传送到多媒体处理器的各个模块。固定功能单元设置在多媒体处理器内，耦合到处理器和数据传输开关。数据流器耦合到数据传输交换机，并且被配置为根据相应的信道分配来调度在多媒体处理器内设置的多个模块之间的同时数据传输。由于接口单元耦合到数据流器并且具有多个I / O设备驱动器单元。耦合到接口单元的多路复用器通过输出引脚提供所选数量的I / O设备驱动器单元和外部I / O设备之间的访问。

8. 发明申请

US20070130401A1 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US20070130401A1
公开(公告)日：2007-06-07
申请号：US11589695
申请日：2006-10-30
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F13/38
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.
摘要翻译：具有多媒体处理器的集成多媒体系统被布置在具有耦合到多媒体处理器的第一主处理器系统的集成电路中，以及设置在多媒体处理器内的用于控制多媒体处理器的操作的第二本地处理器。数据传输开关耦合到第二处理器，用于将数据传送到处理器的各个模块，其中至少一个是数据高速缓存。数据传输交换机在缓存和处理器内的模块之间的任一方向上传输数据。数据流器根据相应的信道分配来调度在多媒体处理器内布置的各个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多个外部I / O设备经由多路复用器耦合到多个I / O设备驱动器单元。

9. 发明授权

US5553002A Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface 失效
公开(公告)号：US5553002A
公开(公告)日：1996-09-03
申请号：US77403
申请日：1993-06-14
申请人： Carlos Dangelo , Richard Deeley , Vijay Nagasamy , Manoucher Vafai
发明人： Carlos Dangelo , Richard Deeley , Vijay Nagasamy , Manoucher Vafai
IPC分类号： G01R31/317 , G01R31/3183 , G06F11/26 , G06F17/50
CPC分类号： G01R31/31704 , G01R31/318357 , G01R31/318364 , G01R31/318378 , G06F11/261 , G06F17/5022 , G06F17/5045
摘要： A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. A top-down design methodology is described, wherein a matrix of milestones (goals in the design activity) is defined by degree of complexity (level of abstraction) of a design and for progressive stages (levels) of design activity (from concept through implementation). The milestones are defined in a monotonic, unidirectional manner using continuous refinement, and the design activity proceeds towards subsequent milestones. As milestones are achieved, previous design activity becomes fixed and unalterable. A feasibility stage is key to convergence of the process. Single level or multi-level estimators (predictors) determine the direction of the process.

10. 发明授权

US06324678B1 Method and system for creating and validating low level description of electronic design 失效
标题翻译：创建和验证电子设计低级描述的方法和系统
公开(公告)号：US06324678B1
公开(公告)日：2001-11-27
申请号：US08701727
申请日：1996-08-22
申请人： Carlos Dangelo , Richard Deeley , Vijay Nagasamy , Manoucher Vafai
发明人： Carlos Dangelo , Richard Deeley , Vijay Nagasamy , Manoucher Vafai
IPC分类号： G06F1750
CPC分类号： G01R31/31704 , G01R31/318357 , G01R31/318364 , G01R31/318378 , G06F11/261 , G06F17/5022 , G06F17/5045
摘要： A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. A matrix of milestones (goals in the design activity) is defined by degree of complexity (level of abstraction) of a design and for progressive stages (levels) of design activity (from concept through implementation). The milestones are defined using continuous refinement, and the design activity proceeds towards subsequent milestones. As milestones are achieved, previous design activity becomes unalterable. A feasibility stage is key to convergence of the process. Single level or multi-level estimators determine the direction of the process.
摘要翻译：公开了一种用于从高级描述和规范生成复杂数字设备的结构描述的方法。该方法使用系统的技术来绘制和实施嵌入原始高级描述意图的语义的一致性。设计活动本质上是在各种级别的设计表示上运行的一系列变革。在每个级别，捕获意图（语义）和正式的软件操作，以得到更详细的级别，描述符合设计目标的硬件。方法的重要特征是：捕获用户的概念，意图，规范，描述，约束和权衡; 建筑分区; 高级别的假设分析; 尺寸估算; 定时估计; 建筑权衡; 概念设计与实施估计; 和时间关闭。该方法包括使用估计器，基于在多个实现的设计上收集的数据，用于在逻辑综合之前对设计进行分区和评估。从结构描述中，容易实现设备的物理实现。里程碑矩阵（设计活动中的目标）由设计的复杂度（抽象度）和设计活动（从概念到实施）的渐进阶段（级别）的程度来定义。里程碑的定义是使用不断的细化，设计活动进行到后续的里程碑。随着里程碑的实现，以前的设计活动变得不可改变。可行性阶段是过程融合的关键。单级或多级估计器确定过程的方向。

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