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1. 发明授权

US06965981B2 Processor including a plurality of computing devices 失效
标题翻译：处理器包括多个计算设备
公开(公告)号：US06965981B2
公开(公告)日：2005-11-15
申请号：US10053683
申请日：2002-01-24
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F9/318 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

2. 发明申请

US20060053271A1 Processor 审中-公开
标题翻译：处理器
公开(公告)号：US20060053271A1
公开(公告)日：2006-03-09
申请号：US11216024
申请日：2005-09-01
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F9/30
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： An object of the present invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：本发明的目的是提供一种能够以少量指令代码执行许多计算的处理器。就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

3. 发明授权

US06401190B1 Parallel computing units having special registers storing large bit widths 失效
标题翻译：具有专用寄存器的并行计算单元存储大的位宽
公开(公告)号：US06401190B1
公开(公告)日：2002-06-04
申请号：US08913840
申请日：1997-09-12
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F1500
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：防止发明的一个目的是提供一种能够以少量指令代码执行许多计算的处理器。就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

4. 发明授权

US5893143A Parallel processing unit with cache memories storing NO-OP mask bits for instructions 失效
标题翻译：并行处理单元具有高速缓存存储器，用于存储用于指令的NO-OP掩码位
公开(公告)号：US5893143A
公开(公告)日：1999-04-06
申请号：US667670
申请日：1996-06-21
申请人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
发明人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0875 , G06F9/3885
摘要： Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.
摘要翻译：每个处理单元110a至110d具有单独的高速缓冲存储器100a至100d。当高速缓冲存储器读取来自主存储器5的指令时，指令字段被分配到高速缓冲存储器。每个高速缓冲存储器由公共控制电路20控制。编译器操作以调度处理，以将要执行的处理集中在特定处理单元上。根据调度处理，根据相应的处理单元与高速缓冲存储器的各个执行率来指定高速缓冲存储器100a至100d的容量。在上述布置中，处理器提供由唯一程序计数器控制的处理单元，并且通过提高高速缓冲存储器的效率来改进处理。此外，处理器通过删除不必要的代码来提高高速缓冲存储器的效率。

5. 发明授权

US5872964A Comparison operating unit and graphic operating system 失效
标题翻译：比较操作单元和图形操作系统
公开(公告)号：US5872964A
公开(公告)日：1999-02-16
申请号：US693896
申请日：1996-08-05
申请人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
发明人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
IPC分类号： G06F7/02 , G06F9/30 , G06F9/305 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/3885
摘要： A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on two data to be compared, kind of comparison operation and result of comparison operation respectively, a second storage unit for storing said two data, kind of comparison operation and result of comparison operation, an operating unit for carrying out a predetermined plurality of kinds of comparison operations for two data, a selecting unit for selecting any one of results of comparison operation, and a processing unit for carrying out a processing of a comparison operation. The processing unit checks a storage destination of two data to be compared, gives the two data to the operating unit, checks a storage destination of a kind of a comparison operation, controls the selecting unit to select a result of an operation corresponding to the kind of comparison operation, and stores the operation result into a storage destination in the second storage unit.
摘要翻译：提供一种用于有效地执行比较操作并且可以防止在管道操作期间在管道中产生干扰的单元。该单元包括：第一存储单元，用于存储关于要比较的两个数据的存储信息，比较操作的种类和比较操作的结果;用于存储所述两个数据的第二存储单元，比较操作的种类和比较操作的结果; 操作单元，用于对两个数据执行预定的多种比较操作;选择单元，用于选择比较结果的任一个;以及处理单元，用于执行比较操作的处理。处理单元检查要比较的两个数据的存储目的地，将两个数据给予操作单元，检查比较操作的种类的存储目的地，控制选择单元选择与该种类对应的操作的结果并将运算结果存储在第二存储单元中的存储目的地。

6. 发明授权

US5870618A Processor and data processor 失效
标题翻译：处理器和数据处理器
公开(公告)号：US5870618A
公开(公告)日：1999-02-09
申请号：US681180
申请日：1996-07-22
申请人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
发明人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
IPC分类号： G06F9/305 , G06F9/30 , G06F9/302 , G06F9/34 , G06F9/38 , G06F9/26
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30101
摘要： An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.
摘要翻译：本发明的目的是提供一种处理器，其可以在高速的数据长度大于寄存器文件的数据长度的数据长度的数据之间进行计算，而不会增加硬件的成本，并且第一长寄存器12和具有位宽度为寄存器堆的位宽度的二倍的第二长寄存器13和用于更新第二长寄存器13的数据的长寄存器更新装置14部分地安装在寄存器堆2和像素计算器当长寄存器更新像素计算指令存储在指令寄存器31中时，长寄存器更新装置14连接第二长寄存器13的数据的一部分和从寄存器文件2读取的数据的一部分，并将它们发送经由选择器15传送到像素计算器11和第二长寄存器13.像素计算器11执行第一长寄存器12的数据和数据gi之间的计算从选择器15发出。

7. 发明授权

US5815696A Pipeline processor including interrupt control system for accurately perform interrupt processing even applied to VLIW and delay branch instruction in delay slot 失效
标题翻译：管道处理器包括中断控制系统，用于准确执行中断处理，甚至应用于VLIW，并延迟延迟槽中的分支指令
公开(公告)号：US5815696A
公开(公告)日：1998-09-29
申请号：US888789
申请日：1997-07-07
申请人： Kazuhiko Tanaka , Tohru Nojiri , Keiji Kojima , Kiyokazu Nishioka , Yoshiki Kurokawa
发明人： Kazuhiko Tanaka , Tohru Nojiri , Keiji Kojima , Kiyokazu Nishioka , Yoshiki Kurokawa
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48
CPC分类号： G06F9/327 , G06F9/30149 , G06F9/3804
摘要： There is provided an instruction supply unit 20 for generating addresses for each instruction when an interrupt occurs, from an interrupted instruction until an instruction to be executed later by the number of instructions contained in a delay slot of the instruction an interrupt control unit 50 for storing each address thus generated, and an instruction executing unit 30 for successively reading out each of the stored addresses from the address of the interrupted address after the interrupt processing is completed. The instruction executing unit 30 executes a branch instruction to the address which is first read out. Thereafter, with respect to the addresses which are read out secondly and subsequently, if the address is the branch destination address of the branch instruction, the instruction executing unit 30 executes the branch instruction to the address, and if the address is not the branch destination address, it executes an NOP instruction. Accordingly, even when the instruction length is not fixed, the interrupt can be accurately processed.
摘要翻译：提供了一个指令提供单元20，用于当中断发生时，从中断指令到稍后执行的指令的指令生成指令的延迟时隙中的指令数量，用于存储每个指令的地址，中断控制单元50用于存储每个地址如此生成，以及指令执行单元30，用于在完成中断处理之后，从中断地址的地址中连续地读出每个存储的地址。指令执行单元30对首先被读出的地址执行分支指令。此后，对于第二次读出的地址，随后，如果地址是分支指令的分支目的地地址，则指令执行单元30对该地址执行分支指令，如果地址不是分支目的地地址，它执行一个NOP指令。因此，即使指令长度不固定，也能够正确地进行中断处理。

8. 发明申请

US20140015656A1 VEHICLE APPROACH ALERT DEVICE FOR SADDLE-RIDDEN ELECTRIC VEHICLE 有权
标题翻译：车载电动车辆方法警报装置
公开(公告)号：US20140015656A1
公开(公告)日：2014-01-16
申请号：US14001635
申请日：2012-02-03
申请人： Satoru Shimizu , Masahiro Akiba , Ryuji Akiba , Kazuhiko Tanaka
发明人： Satoru Shimizu , Masahiro Akiba , Ryuji Akiba , Kazuhiko Tanaka
IPC分类号： B60Q5/00 , B62J3/00
CPC分类号： B60Q5/008 , B60L2270/42 , B60Q1/0017 , B62J3/00 , B62K2202/00 , B62K2204/00 , G10K9/22 , G10K11/004
摘要： A vehicle approach alert device for a saddle-ridden electric vehicle is a vehicle approach alert device for a saddle-ridden electric vehicle that is provided with a sound emitter that is attached on the vehicle body of a saddle-ridden electric vehicle having an electric motor in a power engine, and that emits an alert sound to a surrounding area for notifying the surrounding area of approach of the saddle-ridden electric vehicle, such that sound emission of the sound emitter is controlled, and the sound emitter is arranged so that the direction of sound emission is oriented diagonally downward and forward of the saddle-ridden electric vehicle.
摘要翻译：用于骑马式电动车辆的车辆接近警报装置是用于骑乘式电动车辆的车辆接近警报装置，其具有安装在具有电动马达的骑马式电动车辆的车体上的发声器在电力发动机中，向周围区域发出警报声音，以通知骑乘式电动车辆的周边区域，使得发声器的声音发射被控制，并且发声器被布置成使得发声方向朝向骑马式电动汽车的向下和向前方向。

9. 发明申请

US20120260436A1 NORMAL PRESSURE DYEABLE POLYESTER FIBER AND METHOD FOR PRODUCING THE SAME 审中-公开
标题翻译：普通压力可聚酯纤维及其制造方法
公开(公告)号：US20120260436A1
公开(公告)日：2012-10-18
申请号：US13513716
申请日：2010-12-03
申请人： Kazuhide Oka , Hiroyuki Nakada , Masao Kawamoto , Kazuhiko Tanaka
发明人： Kazuhide Oka , Hiroyuki Nakada , Masao Kawamoto , Kazuhiko Tanaka
IPC分类号： C08G63/16 , D02J1/22 , D06P3/54
CPC分类号： D01F6/84 , C08G63/183 , D01D5/088 , D01D5/12 , D01D10/02 , D01D10/0481 , D06P3/54 , D10B2331/04 , D10B2401/063 , D10B2401/14
摘要： Disclosed is a fiber made of a polyester resin, wherein the polyester resin is a copolymer including a dicarboxylic acid component and a glycol component; of the dicarboxylic acid component, 80 mol % or more is accounted for by a terephthalic acid component, 4.0 to 12.0 mol % is accounted for by a cyclohexane dicarboxylic acid component, and 2.0 to 8.0 mol % is accounted for by an adipic acid component; and the glycol component contains an ethylene glycol component as a main component thereof. A polyester fiber is thereby provided which can be dyed with excellent deep color property and fastness property in dyeing under a normal pressure environment and which can offer stable quality and processing performance also by a direct spinning stretching method or other general melt-spinning methods.
摘要翻译：公开了由聚酯树脂制成的纤维，其中所述聚酯树脂是包含二羧酸组分和二元醇组分的共聚物; 的二羧酸成分，通过对苯二甲酸成分计算为80摩尔％以上，环己烷二羧酸成分占4.0〜12.0摩尔％，己二酸成分占2.0〜8.0摩尔％二醇成分含有乙二醇成分作为主要成分。由此可以提供一种聚酯纤维，其可以在常压环境下染色具有优异的深色性和耐牢度性，并且还可以通过直接纺丝拉伸法或其它一般的熔融纺丝方法提供稳定的质量和加工性能。

10. 发明申请

US20110249039A1 IMAGE DISPLAY DEVICE 有权
标题翻译：图像显示设备
公开(公告)号：US20110249039A1
公开(公告)日：2011-10-13
申请号：US13079076
申请日：2011-04-04
申请人： Yuya OGI , Yasutaka Tsuru , Kazuhiko Tanaka
发明人： Yuya OGI , Yasutaka Tsuru , Kazuhiko Tanaka
IPC分类号： G09G5/10
CPC分类号： G09G3/3426 , G09G3/3611 , G09G2320/0233 , G09G2320/062 , G09G2320/064 , G09G2320/0646 , G09G2330/021 , G09G2360/16
摘要： In a liquid-crystal display device including an edge-light-scheme-employed backlight device, it is implemented to reduce its power consumption while maintaining its excellent picture-quality. The present invention is applied to the backlight device with a plurality of edge-light-scheme backlight cells in a matrix-like manner including a LED light-source, and a light-guiding plate for emitting light. The intensity of light from a backlight cell positioned at a screen's peripheral portion is so controlled as to be made lower than the intensity of light from a backlight cell at a central portion. The light intensity of a backlight cell having a LED light-source adjacent to a first edge portion of the illumination surface of the backlight device is so controlled as to be made higher than the light intensity of a backlight cell adjacent to a second edge portion opposed to the first edge portion.
摘要翻译：在包括边缘照明方案的背光装置的液晶显示装置中，实现了降低其功耗，同时保持其优异的图像质量。本发明以包括LED光源的矩阵状方式和用于发光的导光板应用于具有多个边缘光方案背光单元的背光装置。来自位于屏幕周边部分的背光单元的光的强度被控制得低于在中心部分来自背光单元的光的强度。具有与背光装置的照明面的第一边缘部相邻的LED光源的背光单元的光强度被控制为高于与相对的第二边缘部相邻的背光单元的光强度到第一边缘部分。

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