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1. 发明授权

US08768527B2 Power demand-supply management server and power demand-supply management system 有权
标题翻译：电力需求供应管理服务器和电力需求供应管理系统
公开(公告)号：US08768527B2
公开(公告)日：2014-07-01
申请号：US13061202
申请日：2010-01-08
申请人： Yasushi Tomita , Yasuo Sato , Masahiro Watanabe , Rena Tachihara , Yuichi Otake , Tatsuya Yamada
发明人： Yasushi Tomita , Yasuo Sato , Masahiro Watanabe , Rena Tachihara , Yuichi Otake , Tatsuya Yamada
IPC分类号： G05D17/00
CPC分类号： H02J3/14 , H02J13/0079 , H02J2003/143 , H02J2003/146 , Y02B70/3225 , Y02B70/3266 , Y04S20/222 , Y04S20/224 , Y04S20/242
摘要： A power demand/supply management server (10) obtains information defining restraint contents to a comfort and an electricity bill from a consumer power operating device (2). An individual-consumer control optimizing unit of the power demand/supply management server (10) calculates control contents to an electrical equipment having a minimum cost evaluation value based on a simulation result of cost evaluation values which are barometers for evaluating a comfort and an electricity bill excessiveness, and transmits the calculated control contents to the consumer power operating device (2). Also, a whole-consumer optimizing unit of the power demand/supply management server (10) calculates the most appropriate electricity unit meter-charge that ensures a necessary demand suppression plan level throughout the whole power system based on an electricity daily load curve for each consumer.
摘要翻译：电力需求/供应管理服务器（10）从消费电力操作装置（2）获得定义约束内容到舒适性和电费单的信息。电力需求/供应管理服务器（10）的个人消费者控制优化单元基于作为用于评估舒适度和电力的气压计的成本评估值的模拟结果来计算具有最低成本评估值的电气设备的控制内容票据过多，并将计算出的控制内容发送给消费者电力操作装置（2）。此外，电力需求/供应管理服务器（10）的整体消费者优化单元计算最适合的电力单位计费，其基于每个电力日负荷曲线确保整个电力系统中的必要的需求抑制计划水平消费者。

2. 发明授权

US08749255B2 Electronic device test apparatus 有权
标题翻译：电子设备测试仪器
公开(公告)号：US08749255B2
公开(公告)日：2014-06-10
申请号：US13018726
申请日：2011-02-01
申请人： Yasuhide Takeda , Hiroyuki Nagai , Yoji Ogino , Tatsuya Yamada
发明人： Yasuhide Takeda , Hiroyuki Nagai , Yoji Ogino , Tatsuya Yamada
IPC分类号： G01R31/00 , G01R31/26
CPC分类号： G01R31/2893 , G01R1/0483 , G01R31/2867 , G01R31/2874
摘要： An electronic device test apparatus which can optimize throughput and costs is provided.An electronic device test apparatus 1 comprises: a test cell cluster 10 having cell groups 11A to 11H each of which has a plurality of test cells 20; and a conveyor apparatus 30 supplying test carriers to a plurality of the test cells 20, and each of the test cell 20 has: contactors 215; a flow path 221 connected to a vacuum pump 25 and reducing pressure in a recess 211 of a pocket 21 so as to bring external terminals 73 and the contactors 215 into contact; and a test circuit for running a test on an electronic circuit formed into a die 90.
摘要翻译：提供了可以优化生产量和成本的电子设备测试装置。电子设备测试装置1包括：具有单元组11A至11H的测试单元簇10，每个单元组具有多个测试单元20; 以及向多个测试单元20提供测试载体的传送装置30，并且每个测试单元20具有：接触器215; 连接到真空泵25的流路221，并且减小袋21的凹部211中的压力，使外部端子73和接触器215接触; 以及用于在形成为模具90的电子电路上运行测试的测试电路。

3. 发明授权

US07633153B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07633153B2
公开(公告)日：2009-12-15
申请号：US11778516
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/10
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
摘要翻译：半导体模块包括安装板。多个电源开关器件芯片通过倒装芯片接合安装在安装板上。芯片具有上表面和下表面，并且被配置为面向安装板的上表面。通过倒装芯片接合将驱动IC芯片安装在安装板上。驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。多个散热构件分别位于多个功率开关器件芯片的下表面上。提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

4. 发明授权

US07631234B2 Test apparatus and test method 失效
标题翻译：试验装置及试验方法
公开(公告)号：US07631234B2
公开(公告)日：2009-12-08
申请号：US11589314
申请日：2006-10-27
申请人： Tatsuya Yamada
发明人： Tatsuya Yamada
IPC分类号： G01R31/28 , G11C29/00 , G01R31/26 , H03K19/00
CPC分类号： G01R31/31928 , G11C29/56004
摘要： The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every test period, a plurality of edge generators that respectively generate an edge of a test signal to be supplied to the device under test based on the test pattern every cycle period of a reference clock that is used as a reference for an operation of this test apparatus, a selecting section that selects which edge generator generates each edge of a test signal to be output during the next cycle period based on a pattern of the edge generated during the current cycle period, and a test signal supplying section that supplies the test signal according to each edge generated from the selected edge generator to the device under test.
摘要翻译：本测试装置避免了边缘的接近限制违规，并且肯定地产生测试信号。提供了测试被测设备的测试装置。测试装置包括：测试图形生成部，其生成测试图案，以测试每个测试周期的被测设备;多个边缘发生器，分别产生测试信号的边缘，以供应给被测设备; 对作为该测试装置的操作的基准的参考时钟的周期周期进行模式化;选择部，其选择哪个边沿发生器基于下一个周期期间的图形生成在下一个周期期间输出的测试信号的每个边沿在当前周期期间产生的边缘，以及测试信号提供部分，根据从所选边缘发生器产生的每个边缘将测试信号提供给被测器件。

5. 发明申请

US20080258749A1 TEST APPARATUS, AND ELECTRONIC DEVICE 失效
标题翻译：测试设备和电子设备
公开(公告)号：US20080258749A1
公开(公告)日：2008-10-23
申请号：US11688838
申请日：2007-03-20
申请人： TATSUYA YAMADA
发明人： TATSUYA YAMADA
IPC分类号： G01R31/28
CPC分类号： G01R31/31926
摘要： A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test.
摘要翻译：提供测试被测设备的测试设备。该测试装置包括：主存储器，其存储用于测试被测设备的测试数据行; 缓存从主存储器读取的测试数据行的高速缓冲存储器; 图案生成控制部，读取作为主存储器的数据传送单元的单元不对齐的每个测试数据，并将其写入高速缓冲存储器中对于每个测试数据彼此不同的高速缓存条目; 以及模式生成部，其顺序地读取高速缓冲存储器中的每个高速缓存条目存储的测试数据，并生成用于测试被测设备的测试模式。

6. 发明申请

US20080235549A1 TEST APPARATUS AND ELECTRONIC DEVICE 失效
标题翻译：测试装置和电子设备
公开(公告)号：US20080235549A1
公开(公告)日：2008-09-25
申请号：US11689489
申请日：2007-03-21
申请人： TATSUYA YAMADA
发明人： TATSUYA YAMADA
IPC分类号： G01R31/28
CPC分类号： G01R31/31919 , G01R31/31813 , G11C29/56 , G11C29/56004 , G11C2029/2602 , G11C2029/5602
摘要： There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test. The pattern generating section repeatedly executes an instruction stream within the repeated interval in the test instruction stream when the repeated interval is stored on the interval register.
摘要翻译：提供了测试被测设备的测试装置。测试装置包括存储测试指令流的模式存储器，该测试指令流确定用于测试被测器件的测试序列，间隔寄存器响应于重复间隔显示至少一个要重复执行的指令的事实而存储重复间隔在测试指令流中已经指定了缓存从模式存储器读取的测试指令流的指令高速缓存，从模式存储器读取测试指令流并将读取流写入指令高速缓存的存储器控制部分，模式产生部分，其从指令高速缓存读取并执行包括在测试指令流中的指令，并且生成与执行的指令相对应的测试模式;以及信号输出部分，其基于测试模式生成测试信号，并将产生的信号提供给被测设备。当重复间隔被存储在间隔寄存器上时，模式生成部分在测试指令流中重复执行重复间隔内的指令流。

7. 发明申请

US20070124638A1 Test apparatus and test method 失效
标题翻译：试验装置及试验方法
公开(公告)号：US20070124638A1
公开(公告)日：2007-05-31
申请号：US11589314
申请日：2006-10-27
申请人： Tatsuya Yamada
发明人： Tatsuya Yamada
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31928 , G11C29/56004
摘要： The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every test period, a plurality of edge generators that respectively generate an edge of a test signal to be supplied to the device under test based on the test pattern every cycle period of a reference clock that is used as a reference for an operation of this test apparatus, a selecting section that selects which edge generator generates each edge of a test signal to be output during the next cycle period based on a pattern of the edge generated during the current cycle period, and a test signal supplying section that supplies the test signal according to each edge generated from the selected edge generator to the device under test.
摘要翻译：本测试装置避免了边缘的接近限制违规，并且肯定地产生测试信号。提供了测试被测设备的测试装置。测试装置包括：测试图形生成部，其生成测试图案，以测试每个测试周期的被测设备;多个边缘发生器，分别产生测试信号的边缘，以供应给被测设备; 对作为该测试装置的操作的基准的参考时钟的周期周期进行模式化;选择部，其选择哪个边沿发生器基于下一个周期期间的图形生成在下一个周期期间输出的测试信号的每个边沿在当前周期期间产生的边缘，以及测试信号提供部分，根据从所选边缘发生器产生的每个边缘将测试信号提供给被测器件。

8. 发明授权

US07041718B2 Polyacetal resin composition and moldings 失效
公开(公告)号：US07041718B2
公开(公告)日：2006-05-09
申请号：US10655034
申请日：2003-09-05
申请人： Hatsuhiko Harashina , Hayato Kurita , Tatsuya Yamada
发明人： Hatsuhiko Harashina , Hayato Kurita , Tatsuya Yamada
IPC分类号： C08K5/34
CPC分类号： C08K5/3445 , C08L59/00
摘要： The polyacetal resin composition contains about 0.01–10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01–10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.

9. 发明授权

US6008105A Method of planarizing an insulator film using multiple etching steps 失效
标题翻译：使用多个蚀刻步骤平坦化绝缘膜的方法
公开(公告)号：US6008105A
公开(公告)日：1999-12-28
申请号：US151288
申请日：1998-09-11
申请人： Takaaki Ukeda , Tatsuya Yamada , Yoshiaki Kato , Akio Miyajima
发明人： Takaaki Ukeda , Tatsuya Yamada , Yoshiaki Kato , Akio Miyajima
IPC分类号： G03F7/11 , G03F1/68 , G03F1/80 , G03F7/00 , G03F7/40 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/28
CPC分类号： H01L21/31055 , G03F1/70 , G03F7/0035
摘要： The semiconductor masking device of the invention includes a first semiconductor mask for forming an interconnection on a semiconductor substrate and a second semiconductor mask for forming a resist pattern on an insulating film. The first semiconductor mask has three masking areas and the second semiconductor mask has two masking areas. Masking area intervals, that is, the distances between the three masking areas of the first semiconductor mask and the two masking areas of the second semiconductor mask, are all equal to one another.
摘要翻译：本发明的半导体掩模装置包括用于在半导体衬底上形成互连的第一半导体掩模和用于在绝缘膜上形成抗蚀剂图案的第二半导体掩模。第一半导体掩模具有三个掩蔽区域，第二半导体掩模具有两个掩蔽区域。掩蔽区间隔，即第一半导体掩模的三个屏蔽区域与第二半导体掩模的两个屏蔽区域之间的距离都彼此相等。

10. 发明授权

US08700964B2 Test apparatus and synchronization method 有权
标题翻译：测试仪器和同步方法
公开(公告)号：US08700964B2
公开(公告)日：2014-04-15
申请号：US13029065
申请日：2011-02-16
申请人： Tatsuya Yamada
发明人： Tatsuya Yamada
IPC分类号： G01R31/28
CPC分类号： G01R31/31726 , G01R31/31922
摘要： A test apparatus that tests a device under test, including (i) a master domain that includes a master period signal generating section, which generates a master period signal, where the master domain operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, where the slave domain operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is on hold, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is on hold.
摘要翻译：一种测试被测设备的测试装置，包括：（i）包括主周期信号产生部分的主域，其产生主时段信号，其中主域基于主周期信号操作，以及（ii）从属域，其包括从周期信号生成部分，其产生从周期信号，其中从属域基于从周期信号操作。主周期信号发生部分接收控制信号并恢复保持的主周期信号的产生，从周期信号产生部分接收控制信号，初始化从周期信号的相位数据，并恢复生成从周期信号，其保持。

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