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1. 发明授权

US08700964B2 Test apparatus and synchronization method 有权
标题翻译：测试仪器和同步方法
公开(公告)号：US08700964B2
公开(公告)日：2014-04-15
申请号：US13029065
申请日：2011-02-16
申请人： Tatsuya Yamada
发明人： Tatsuya Yamada
IPC分类号： G01R31/28
CPC分类号： G01R31/31726 , G01R31/31922
摘要： A test apparatus that tests a device under test, including (i) a master domain that includes a master period signal generating section, which generates a master period signal, where the master domain operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, where the slave domain operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is on hold, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is on hold.
摘要翻译：一种测试被测设备的测试装置，包括：（i）包括主周期信号产生部分的主域，其产生主时段信号，其中主域基于主周期信号操作，以及（ii）从属域，其包括从周期信号生成部分，其产生从周期信号，其中从属域基于从周期信号操作。主周期信号发生部分接收控制信号并恢复保持的主周期信号的产生，从周期信号产生部分接收控制信号，初始化从周期信号的相位数据，并恢复生成从周期信号，其保持。

2. 发明授权

US08502523B2 Test apparatus and test method 失效
标题翻译：试验装置及试验方法
公开(公告)号：US08502523B2
公开(公告)日：2013-08-06
申请号：US13024264
申请日：2011-02-09
申请人： Tatsuya Yamada
发明人： Tatsuya Yamada
IPC分类号： G01R23/00
CPC分类号： G01R31/31922
摘要： Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains. The test apparatus comprises a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain.
摘要翻译：提供了一种用于基本上同步多个时钟域中的每一个的测试信号的相位的测试装置和测试方法。测试装置测试包括多个时钟域的被测器件。测试装置包括周期发生器，其产生用于确定对应于被测器件的操作周期的测试周期的速率信号; 生成测试图案的图案生成器; 相位比较部，对于每个时钟域，接收从被包括在时钟域中的被测器件的端子获取的时钟域的操作时钟信号，并且相对于时钟域的操作时钟信号的相位差相对于到速率信号; 以及多个波形整形部分，分别设置在时钟域上，并且根据相应的时钟域的相位差，基于测试图形来形成测试信号，以使测试信号与操作时钟基本上同步相应时钟域的信号。

3. 发明申请

US20110282505A1 POWER DEMAND-SUPPLY MANAGEMENT SERVER AND POWER DEMAND-SUPPLY MANAGEMENT SYSTEM 有权
标题翻译：电力需求管理服务器和电力需求管理系统
公开(公告)号：US20110282505A1
公开(公告)日：2011-11-17
申请号：US13061202
申请日：2010-01-08
申请人： Yasushi Tomita , Yasuo Sato , Masahiro Watanabe , Rena Tachihara , Yuichi Otake , Tatsuya Yamada
发明人： Yasushi Tomita , Yasuo Sato , Masahiro Watanabe , Rena Tachihara , Yuichi Otake , Tatsuya Yamada
IPC分类号： G06F1/32
CPC分类号： H02J3/14 , H02J13/0079 , H02J2003/143 , H02J2003/146 , Y02B70/3225 , Y02B70/3266 , Y04S20/222 , Y04S20/224 , Y04S20/242
摘要： A power demand/supply management server (10) obtains information defining restraint contents to a comfort and an electricity bill from a consumer power operating device (2). An individual-consumer control optimizing unit of the power demand/supply management server (10) calculates control contents to an electrical equipment having a minimum cost evaluation value based on a simulation result of cost evaluation values which are barometers for evaluating a comfort and an electricity bill excessiveness, and transmits the calculated control contents to the consumer power operating device (2). Also, a whole-consumer optimizing unit of the power demand/supply management server (10) calculates the most appropriate electricity unit meter-charge that ensures a necessary demand suppression plan level throughout the whole power system based on an electricity daily load curve for each consumer.
摘要翻译：电力需求/供应管理服务器（10）从消费电力操作装置（2）获得定义约束内容到舒适性和电费单的信息。电力需求/供应管理服务器（10）的个人消费者控制优化单元基于作为用于评估舒适度和电力的气压计的成本评估值的模拟结果来计算具有最低成本评估值的电气设备的控制内容票据过多，并将计算出的控制内容发送给消费者电力操作装置（2）。此外，电力需求/供应管理服务器（10）的整体消费者优化单元计算最适合的电力单位计费，其基于每个电力日负荷曲线确保整个电力系统中的必要的需求抑制计划水平消费者。

4. 发明申请

US20110161763A1 TEST APPARATUS AND SYNCHRONIZATION METHOD 有权
标题翻译：测试装置和同步方法
公开(公告)号：US20110161763A1
公开(公告)日：2011-06-30
申请号：US13029065
申请日：2011-02-16
申请人： Tatsuya YAMADA
发明人： Tatsuya YAMADA
IPC分类号： G01R31/3183 , G06F11/22
CPC分类号： G01R31/31726 , G01R31/31922
摘要： Provided is a test apparatus that tests a device under test, comprising (i) a master domain that includes a master period signal generating section, which generates a master period signal, and that operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, and that operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is being held, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is being held.
摘要翻译：提供了一种测试被测设备的测试装置，包括：（i）主域，其包括主周期信号生成部分，其生成主周期信号，并且基于主周期信号进行操作;以及（ii）从机域，其包括从周期信号生成部分，其产生从周期信号，并且其基于从周期信号进行操作。主时段信号发生部分接收控制信号并恢复正在保持的主周期信号的产生，从周期信号产生部分接收控制信号，初始化从周期信号的相位数据，并恢复生成从时期信号，正在举行。

5. 发明授权

US07725793B2 Pattern generation for test apparatus and electronic device 有权
标题翻译：测试仪器和电子设备的图案生成
公开(公告)号：US07725793B2
公开(公告)日：2010-05-25
申请号：US11689506
申请日：2007-03-21
申请人： Tatsuya Yamada , Tomoyuki Sugaya
发明人： Tatsuya Yamada , Tomoyuki Sugaya
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31919 , G01R31/31813
摘要： There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed, a pattern generating section that (i) sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction and (II) timing set information designating a combination of timings for output of the test pattern, (ii) under a condition of executing the subroutine call instruction, sequentially reads and executes an instruction from the sub test instruction sequence designated by the executed subroutine call instruction and outputs (1) a test pattern associated with the executed instruction and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence, and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information.
摘要翻译：提供了一种用于测试被测设备的测试装置。测试装置包括：主指令存储部分，其上存储有主测试指令序列;子指令存储部分，其存储当执行包括在主测试指令序列中的子程序调用指令时执行的子测试指令序列; （i）顺序读取并执行来自主测试指令序列的指令，并且输出（I）与所执行的指令相关联的测试模式;以及（II）指定用于输出测试模式的定时的组合的定时设置信息，（ii）在执行子程序调用指令的条件下，顺序地从由执行的子程序调用指令指定的子测试指令序列读取并执行指令，并输出（1）与执行的指令相关联的测试模式，（2）与子程序调用指令相关联的测试模式的定时设置信息或在主测试指令序列中的子程序调用指令之前的指令以及根据测试模式产生测试信号的测试信号输出部分，并且在由定时设定的定时将测试信号提供给被测器件信息。

6. 发明授权

US07696730B2 Control apparatus for AC-AC converter 失效
标题翻译： AC-AC转换器控制装置
公开(公告)号：US07696730B2
公开(公告)日：2010-04-13
申请号：US11882283
申请日：2007-07-31
申请人： Yasuhiro Tamai , Tatsuya Yamada
发明人： Yasuhiro Tamai , Tatsuya Yamada
IPC分类号： H02J3/08 , H02J3/00
CPC分类号： H02M5/27
摘要： A control apparatus for an AC-AC direct converter. The control apparatus includes a calculator providing a phase command θ* of an output voltage of the converter, a calculator providing a q-axis current iq by using output currents iu and iw and the phase command θ*, a detector detecting a pulsation component contained in the q-axis current iq, a calculator providing a phase correction magnitude θcmp so as to decrease the pulsation component, and an adder/subtractor correcting the phase command θ* by using the correction magnitude θcmp. This apparatus can decrease the output voltage distortion and low frequency torque pulsation and can suppress the increase of an output current without weakening a magnetic flux, even when the converter is operated in an overmodulation region.
摘要翻译：一种用于AC-AC直接转换器的控制装置。控制装置包括：计算器，其提供转换器的输出电压的相位指令和*，通过使用输出电流iu和iw以及相位指令＆amp;等提供q轴电流iq的计算器; *，检测脉动的检测器分量包含在q轴电流iq中，计算器提供相位校正幅度＆amp; cmp，以减小脉动分量;以及加法器/减法器，通过使用校正幅度＆amp; cmp校正相位指令。该装置可以降低输出电压失真和低频转矩脉动，并且即使当转换器在过调制区域中操作时也可以抑制输出电流的增加而不削弱磁通量。

7. 发明申请

US20080250291A1 TEST APPARATUS AND ELECTRONIC DEVICE 失效
标题翻译：测试装置和电子设备
公开(公告)号：US20080250291A1
公开(公告)日：2008-10-09
申请号：US11733174
申请日：2007-04-09
申请人： Tatsuya Yamada , Kiyoshi Murata
发明人： Tatsuya Yamada , Kiyoshi Murata
IPC分类号： G01R31/3183
CPC分类号： G01R31/31813
摘要： A test apparatus that tests a device under test is provided.The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.
摘要翻译：提供测试被测设备的测试设备。测试装置包括：模式存储器，以压缩格式存储测试指令序列，以定义用于测试被测设备的测试序列; 扩展部分块以非压缩格式扩展从模式存储器读取的测试指令序列; 缓存由扩展部扩展的测试指令序列的指令高速缓存; 模式生成部，其顺序地读取存储在所述指令高速缓存中的指令，并执行所述指令，以生成所执行的指令的测试模式; 以及信号输出部，其基于测试图案生成测试信号，并将其提供给被测设备。

8. 发明申请

US20080235550A1 TEST APPARATUS AND ELECTRONIC DEVICE 有权
标题翻译：测试装置和电子设备
公开(公告)号：US20080235550A1
公开(公告)日：2008-09-25
申请号：US11689506
申请日：2007-03-21
申请人： TATSUYA YAMADA , Tomoyuki Sugaya
发明人： TATSUYA YAMADA , Tomoyuki Sugaya
IPC分类号： G01R31/317
CPC分类号： G01R31/31919 , G01R31/31813
摘要： There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed, a pattern generating section that (i) sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction and (II) timing set information designating a combination of timings for output of the test pattern, (ii) under a condition of executing the subroutine call instruction, sequentially reads and executes an instruction from the sub test instruction sequence designated by the executed subroutine call instruction and outputs (1) a test pattern associated with the executed instruction and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence, and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information.
摘要翻译：提供了一种用于测试被测设备的测试装置。测试装置包括：主指令存储部分，其上存储有主测试指令序列;子指令存储部分，其存储当执行包括在主测试指令序列中的子程序调用指令时执行的子测试指令序列; （i）顺序读取并执行来自主测试指令序列的指令，并且输出（I）与所执行的指令相关联的测试模式;以及（II）指定用于输出测试模式的定时的组合的定时设置信息，（ii）在执行子程序调用指令的条件下，顺序地从由执行的子程序调用指令指定的子测试指令序列读取并执行指令，并输出（1）与执行的指令相关联的测试模式，（2）与子程序调用指令相关联的测试模式的定时设置信息或在主测试指令序列中的子程序调用指令之前的指令以及根据测试模式产生测试信号的测试信号输出部分，并且在由定时设定的定时将测试信号提供给被测器件信息。

9. 发明申请

US20080235539A1 TEST APPARATUS AND ELECTRONIC DEVICE 有权
标题翻译：测试装置和电子设备
公开(公告)号：US20080235539A1
公开(公告)日：2008-09-25
申请号：US11689483
申请日：2007-03-21
申请人： TATSUYA YAMADA
发明人： TATSUYA YAMADA
IPC分类号： G06F11/00
CPC分类号： G01R31/31919 , G01R31/31813
摘要： There is provided a test apparatus that tests a device under test. The test apparatus includes a main memory that stores a test instruction stream determining a test sequence for testing the device under test, a sequence cache memory that caches the test instruction stream, a transfer section that reads the test instruction stream stored on the main memory and writes the read stream into the sequence cache memory in accordance with a described sequence, a pattern generating section that sequentially reads and executes instructions from the test instruction stream cached on the sequence cache memory and outputs a test pattern corresponding to the executed instruction, and a test signal output section that generates a test signal according to the test pattern and supplies the generated signal to the device under test, in which the transfer section overwrites the instruction read from the main memory on a space area on the sequence cache memory or an area on which executed instructions are stored and prohibits overwriting the read instruction on an area on which instructions in a predetermined range is stored, the instructions being located in the predetermined range forward from a final instruction among the executed instructions according to the described sequence.
摘要翻译：提供了测试被测设备的测试装置。该测试装置包括：主存储器，存储确定用于测试被测设备的测试序列的测试指令流;缓存测试指令流的顺序高速缓存存储器;读取存储在主存储器上的测试指令流的传送部分;以及根据所描述的顺序将读取流写入序列高速缓存存储器，模式生成部分，其顺序地从缓存在序列高速缓冲存储器上的测试指令流读取并执行指令，并输出与执行的指令相对应的测试模式，测试信号输出部分，其根据测试模式产生测试信号，并将生成的信号提供给被测器件，其中传输部分在序列高速缓存存储器上的空间区域上覆盖从主存储器读取的指令，或者区域在其上存储执行的指令，并禁止覆盖区域上的读取指令在预定范围内存储指令的情况下，根据所描述的顺序，指令位于执行指令中的最终指令之前的预定范围内。

10. 发明申请

US20080235498A1 TEST APPARATUS AND ELECTRONIC DEVICE 失效
标题翻译：测试装置和电子设备
公开(公告)号：US20080235498A1
公开(公告)日：2008-09-25
申请号：US11689503
申请日：2007-03-21
申请人： TATSUYA YAMADA
发明人： TATSUYA YAMADA
IPC分类号： G06F9/30
CPC分类号： G01R31/31919 , G01R31/31813
摘要： There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits. Here, the instruction storing section stores thereon the test instruction sequence including therein a result register update instruction to update a value of a designated bit position in the result register with a predetermined value, and when executing the result register update instruction, the pattern generating section updates, with the predetermined value, the value of the bit position in the result register which is designated by the result register update instruction.
摘要翻译：提供了一种用于测试被测设备的测试装置。测试装置包括存储测试指令序列的指令存储部分，顺序地从测试指令序列读取并执行指令的模式产生部分，并输出与执行指令相关联的测试模式;测试信号输出部分，根据测试模式生成测试信号，并将生成的测试信号提供给被测器件，以及结果寄存器，其中存储具有预定位数的值。这里，指令存储部分在其上存储测试指令序列，其中包括结果寄存器更新指令，用于以预定值更新结果寄存器中的指定位位置的值，并且当执行结果寄存器更新指令时，模式生成部分以预定值更新由结果寄存器更新指令指定的结果寄存器中的位位置的值。

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