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1. 发明授权

US07838424B2 Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching 有权
标题翻译：使用干蚀刻提高晶圆级芯片级封装（WLCSP）芯片分离的可靠性
公开(公告)号：US07838424B2
公开(公告)日：2010-11-23
申请号：US11773277
申请日：2007-07-03
申请人： Tjandra Winata Karta , Steven Hsu , Chien-Hsiun Lee , Gene Wu , Jimmy Liang
发明人： Tjandra Winata Karta , Steven Hsu , Chien-Hsiun Lee , Gene Wu , Jimmy Liang
IPC分类号： H01L21/302
CPC分类号： H01L23/3178 , H01L21/561 , H01L23/3114 , H01L23/3185 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/13023 , H01L2224/16 , H01L2224/94 , H01L2924/01078 , H01L2924/01079 , H01L2924/10157 , H01L2924/14 , H01L2224/03 , H01L2224/11
摘要： An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.
摘要翻译：描述了改进的晶片级芯片级封装（WLCSP）工艺，其包括在半导体晶片的第一表面上形成多个导电柱。将一个或多个凹槽干蚀刻到半导体晶片的第一表面中，其中凹槽限定半导体晶片内的多个裸片中的每一个之间的至少一个边界。一层封装材料沉积在第一表面上。然后通过封装材料在每个凹槽中切割凹部，其中切割在半导体晶片的第二表面上留下一片半导体材料。然后将第二表面研磨以去除该半导体材料片，其中该材料的去除分离多个管芯。

2. 发明授权

US07642129B2 Ball-mounting method for coplanarity improvement in large package 失效
标题翻译：大包装球面安装方法的共面性改善
公开(公告)号：US07642129B2
公开(公告)日：2010-01-05
申请号：US11648926
申请日：2007-01-03
申请人： Jimmy Liang , Gene Wu , Steven Hsu
发明人： Jimmy Liang , Gene Wu , Steven Hsu
IPC分类号： H01L21/00
CPC分类号： H05K3/3457 , H01L21/4853 , H01L2224/16 , H01L2924/14 , H01L2924/15311 , H01L2924/3511 , H05K2203/0278 , H05K2203/043
摘要： A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.
摘要翻译：提供一种形成包装结构的方法及其形成的包装。该方法包括提供具有顶表面的封装并将焊球放置在封装的顶表面上。然后将共面表面放置在焊球上，其中该表面是非粘合的。对焊球进行回流处理，使得焊球的顶表面基本上共面。然后去除共面。

3. 发明申请

US20090102021A1 Through-Silicon Vias and Methods for Forming the Same 有权
标题翻译：通硅通孔和形成方法
公开(公告)号：US20090102021A1
公开(公告)日：2009-04-23
申请号：US11874009
申请日：2007-10-17
申请人： Chih-Hua Chen , Chen-Shien Chen , Chen-Cheng Kuo , Kuo-Ching Steven Hsu , Kai-Ming Ching
发明人： Chih-Hua Chen , Chen-Shien Chen , Chen-Cheng Kuo , Kuo-Ching Steven Hsu , Kai-Ming Ching
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/03 , H01L24/05 , H01L2221/6834 , H01L2224/0401 , H01L2224/0557 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/13009 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2224/05552
摘要： An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.
摘要翻译：提供一种集成电路结构及其形成方法。集成电路结构包括基板; 穿过硅基通孔（TSV）延伸到衬底中; 与TSV间隔开的TSV垫; 以及金属线，并且电连接TSV和TSV焊盘。

4. 发明申请

US20080181295A1 Method and apparatus for video processing 有权
标题翻译：视频处理方法和装置
公开(公告)号：US20080181295A1
公开(公告)日：2008-07-31
申请号：US11699241
申请日：2007-01-29
申请人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
发明人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
IPC分类号： H04B1/66
CPC分类号： H04N19/436 , H04N19/43
摘要： In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括使用冗余二进制数学压缩视频数据的方法。描述和要求保护其他实施例。

5. 发明申请

US20070147158A1 Memory with spatially encoded data storage 有权
标题翻译：内存空间编码数据存储
公开(公告)号：US20070147158A1
公开(公告)日：2007-06-28
申请号：US11321366
申请日：2005-12-28
申请人： Steven Hsu , Atul Maheshwari , Ram Krishnamurthy
发明人： Steven Hsu , Atul Maheshwari , Ram Krishnamurthy
IPC分类号： G11C5/14
CPC分类号： G11C7/1006 , G11C7/22 , G11C7/222 , G11C2207/2227
摘要： Disclosed herein are memory circuit embodiments to have spatially encoded data.
摘要翻译：这里公开了具有空间编码数据的存储器电路实施例。

6. 发明申请

US20060186924A1 Voltage-level converter 有权
公开(公告)号：US20060186924A1
公开(公告)日：2006-08-24
申请号：US11411647
申请日：2006-04-26
申请人： Steven Hsu , Mark Anders , Ram Krishnamurthy
发明人： Steven Hsu , Mark Anders , Ram Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

7. 发明申请

US20060044013A1 Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors 有权
标题翻译：用于多Vcc微处理器的混合CVSL门限电平转换时序电路
公开(公告)号：US20060044013A1
公开(公告)日：2006-03-02
申请号：US10924906
申请日：2004-08-25
申请人： Steven Hsu , Ram Krishnamurthy
发明人： Steven Hsu , Ram Krishnamurthy
IPC分类号： H03K19/0175
CPC分类号： H03K3/356156
摘要： A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.
摘要翻译：逻辑电路通过驱动具有不同电源电压的电路的部分来执行内部电平转换功能。在一个实施例中，第一和第二级存储电路以不同的电源电压驱动。在另一个实施例中，用第一电源电压驱动第一和第二级存储电路，并且以第二电源电压驱动耦合到第一级存储电路的反相器。在这两种情况下，可以通过时钟信号的不同状态来控制对存储电路的数据传输。逻辑电路可以是触发器电路，锁存电路或另一种类型的电路。

8. 发明申请

US20050285624A1 Hybrid pass gate level converting dual supply sequential circuit 审中-公开
标题翻译：混合通门电平转换双电源时序电路
公开(公告)号：US20050285624A1
公开(公告)日：2005-12-29
申请号：US10880751
申请日：2004-06-29
申请人： Steven Hsu , Amit Agarwal , Ram Krishnamurthy
发明人： Steven Hsu , Amit Agarwal , Ram Krishnamurthy
IPC分类号： H03K3/356 , H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356147 , H03K3/356156
摘要： A device comprising a receiving circuit to receive an input signal, a voltage level converting circuit and a biasing circuit. The receiving circuit including an output and a first latch circuit coupled to a first supply node. The voltage level converting circuit includes a second latch circuit coupled to a second supply node, the second latch circuit including cross-coupled logic gates connected between first and second circuit nodes. The second supply node has a voltage level different from the first supply node. The biasing circuit has an input coupled to the receiving circuit output, and also has first and second outputs connectable to bias the first and second circuit nodes of the second latch circuit to complementary logic states based on the receiving circuit output.
摘要翻译：一种装置，包括用于接收输入信号的接收电路，电压电平转换电路和偏置电路。接收电路包括耦合到第一电源节点的输出端和第一锁存电路。电压电平转换电路包括耦合到第二电源节点的第二锁存电路，第二锁存电路包括连接在第一和第二电路节点之间的交叉耦合逻辑门。第二供电节点具有与第一供电节点不同的电压电平。偏置电路具有耦合到接收电路输出的输入，并且还具有可连接的第一和第二输出，以便基于接收电路输出将第二锁存电路的第一和第二电路节点偏置为互补逻辑状态。

9. 发明申请

US20050104612A1 Current mirror multi-channel leakage current monitor circuit and method 有权
标题翻译：电流镜多通道漏电流监测电路及方法
公开(公告)号：US20050104612A1
公开(公告)日：2005-05-19
申请号：US11022800
申请日：2004-12-28
申请人： Steven Hsu , Ram Krishnamurthy , Chris Kim
发明人： Steven Hsu , Ram Krishnamurthy , Chris Kim
IPC分类号： G01R31/30 , G11C29/50 , G01R31/02
CPC分类号： G11C29/50 , G01R31/3012 , G11C2029/5004 , G11C2029/5006
摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.
摘要翻译：电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。

10. 发明授权

US08476769B2 Through-silicon vias and methods for forming the same 有权
标题翻译：硅通孔及其形成方法
公开(公告)号：US08476769B2
公开(公告)日：2013-07-02
申请号：US11874009
申请日：2007-10-17
申请人： Chih-Hua Chen , Chen-Shien Chen , Chen-Cheng Kuo , Kuo-Ching “Steven” Hsu , Kai-Ming Ching
发明人： Chih-Hua Chen , Chen-Shien Chen , Chen-Cheng Kuo , Kuo-Ching “Steven” Hsu , Kai-Ming Ching
IPC分类号： H01L29/01
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/03 , H01L24/05 , H01L2221/6834 , H01L2224/0401 , H01L2224/0557 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/13009 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2224/05552
摘要： An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.
摘要翻译：提供一种集成电路结构及其形成方法。集成电路结构包括基板; 穿过硅基通孔（TSV）延伸到衬底中; 与TSV间隔开的TSV垫; 以及金属线，并且电连接TSV和TSV焊盘。

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