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1. 发明申请

US20230028475A1 PACKAGE IO ESCAPE ROUTING ON A DISAGGREGATED SHORELINE 有权
公开(公告)号：US20230028475A1
公开(公告)日：2023-01-26
申请号：US17957204
申请日：2022-09-30
申请人： Ankireddy Nalamalpu , Mahesh K. Kumashikar , Atul Maheshwari , Lai Guan Tang
发明人： Ankireddy Nalamalpu , Mahesh K. Kumashikar , Atul Maheshwari , Lai Guan Tang
IPC分类号： H01L23/538 , H01L23/498 , H03K19/17736 , H03K19/1776 , H01L25/065
摘要： A system includes a first die having a first side with first die-to-die circuitry and first input output circuitry. The system also includes a second die comprising a second side with second die-to-die circuitry and second input output circuitry. The first and second sides are adjacent to each other in the electronic package device. The system also includes a semiconductor interconnect including multiple connections to interconnect the first and second die-to-die circuitries. The semiconductor interconnect also includes multiple through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge.

2. 发明申请

US20220337250A1 Three-Dimensional Columnar Input-Output (IO) Circuitry for Integrated Circuit Device 有权
公开(公告)号：US20220337250A1
公开(公告)日：2022-10-20
申请号：US17856479
申请日：2022-07-01
申请人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , Atul Maheshwari , Lai Guan Tang
发明人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , Atul Maheshwari , Lai Guan Tang
IPC分类号： H03K19/17736 , H03K19/1776 , H03K19/17728
摘要： This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.

3. 发明申请

US20220229941A1 SECURITY ON DIE-TO-DIE INTERCONNECT 有权
公开(公告)号：US20220229941A1
公开(公告)日：2022-07-21
申请号：US17711779
申请日：2022-04-01
申请人： Lai Guan Tang , Ankireddy Nalamalpu , Mahesh K. Kumashikar , Atul Maheshwari
发明人： Lai Guan Tang , Ankireddy Nalamalpu , Mahesh K. Kumashikar , Atul Maheshwari
IPC分类号： G06F21/85 , G06F21/60 , G06F21/78 , G06F11/07
摘要： Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.

4. 发明授权

US08314725B2 On-die digital-to-analog conversion testing 有权
标题翻译：模数转换测试
公开(公告)号：US08314725B2
公开(公告)日：2012-11-20
申请号：US12883125
申请日：2010-09-15
申请人： Paola Zepeda , David E. Duarte , Gregory F. Taylor , Atul Maheshwari
发明人： Paola Zepeda , David E. Duarte , Gregory F. Taylor , Atul Maheshwari
IPC分类号： H03M1/10
CPC分类号： H03M1/109 , H03M1/12
摘要： In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit 370 can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，通过片上测试电路来评估集成电路中的模数转换。例如，片上测试电路370可以表征数模转换的线性度和单调性之一或两者。数字输入代码的转换输出的值可以与先前步骤的先前转换输出的值进行比较，以为扫描数字输入代码的每个步骤提供数字差值。可以将数字差值与一个或多个预定限制进行比较，以在芯片上提供一个或多个通过/失败测试。描述和要求保护其他实施例。

5. 发明申请

US20220337251A1 SYSTEMS AND METHODS FOR MODULAR DISAGGREGATED INTEGRATED CIRCUIT SYSTEMS 有权
公开(公告)号：US20220337251A1
公开(公告)日：2022-10-20
申请号：US17856643
申请日：2022-07-01
申请人： Ankireddy Nalamalpu , Mahesh K. Kumashikar , Atul Maheshwari , Lai Guan Tang
发明人： Ankireddy Nalamalpu , Mahesh K. Kumashikar , Atul Maheshwari , Lai Guan Tang
IPC分类号： H03K19/17796 , G06F30/347 , H03K19/17736 , H01L25/065
摘要： Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.

6. 发明申请

US20220013488A1 Homogenous Die Stacking With Increased Element Density 有权
公开(公告)号：US20220013488A1
公开(公告)日：2022-01-13
申请号：US17484922
申请日：2021-09-24
申请人： Mahesh K. Kumashikar , Dheeraj Subbareddy , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
发明人： Mahesh K. Kumashikar , Dheeraj Subbareddy , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
IPC分类号： H01L23/00 , H01L25/065 , H01L23/48 , H01L25/00
摘要： An integrated circuit device includes multiple microbumps and a top programmable fabric die including a first programmable fabric and a first microbump interface coupled to the multiple microbumps. The integrated circuit device also includes a base programmable fabric die having a second programmable fabric and a second microbump interface coupled to the first microbump interface via a coupling to the multiple microbumps. The top programmable fabric die and the base programmable fabric die have a same design. Moreover, the top programmable fabric die and the base programmable fabric die are arranged in a three-dimensional die arrangement with the top programmable fabric die flipped above the base programmable fabric die.

7. 发明申请

US20140340129A1 FREQUENCY CONTROL SYSTEM WITH DUAL-INPUT BIAS GENERATOR TO SEPARATELY RECEIVE MANAGEMENT AND OPERATIONAL CONTROLS 有权
标题翻译：具有双输入偏置发电机的频率控制系统，以分别接收管理和运行控制
公开(公告)号：US20140340129A1
公开(公告)日：2014-11-20
申请号：US13977424
申请日：2012-04-13
申请人： Atul Maheshwari , Parker J. Rachel , Kuan-Yueh James Shen
发明人： Atul Maheshwari , Parker J. Rachel , Kuan-Yueh James Shen
IPC分类号： H03L7/16 , H03L7/08
CPC分类号： H03L7/16 , H03L7/0802 , H03L7/0893 , H03L7/0895 , H03L7/093 , H03L7/099 , H03L7/1072 , H03L2207/06
摘要： Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode.
摘要翻译：控制相对于参考频率的输出频率的方法和系统。频率控制系统包括双输入偏置发生器，用于分别接收管理和操作控制。偏置发生器包括：第一偏置发生器电路，用于在第一操作模式期间基于管理控制和偏置反馈参考之间的差异产生偏置控制;第二偏置发生器电路，用于基于第一偏置发生器电路之间的差产生偏置控制; 在第二操作模式期间的操作控制和偏置反馈参考，以及偏置反馈参考电路，以基于偏置控制产生偏置反馈参考。第一模式可以包括表征和/或启动模式。第二模式可以包括诸如反馈控制模式的操作模式。

8. 发明授权

US07471102B2 Measuring threshold voltage of transistors in a circuit 有权
公开(公告)号：US07471102B2
公开(公告)日：2008-12-30
申请号：US11710359
申请日：2007-02-23
申请人： Atul Maheshwari , Greg Taylor
发明人： Atul Maheshwari , Greg Taylor
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2884 , G01R31/2621
摘要： In one embodiment, the present invention includes an oscillator to generate a first frequency and a second frequency. The oscillator includes a plurality of stage cells, each stage cell including a first transistor of a first polarity and a second transistor of a second polarity, each coupled between a first voltage node and a first intermediate node and an inverter coupled to the first intermediate node. In operation, a difference between the first frequency and the second frequency is proportional to a threshold voltage of the second transistor. Other embodiments are described and claimed.

9. 发明授权

US07332937B2 Dynamic logic with adaptive keeper 有权
标题翻译：动态逻辑与自适应守门员
公开(公告)号：US07332937B2
公开(公告)日：2008-02-19
申请号：US11321328
申请日：2005-12-28
申请人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , G01R31/3008 , G01R31/31721 , H03K19/00361 , H03K19/00384
摘要： Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.
摘要翻译：这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。在一些实施例中，可编程保持器电路耦合到寄存器文件电路。包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。要求保护或以其他方式公开其他实施例。

10. 发明授权

US07279939B2 Circuit for differential current sensing with reduced static power 有权
标题翻译：具有降低静态功耗的差分电流检测电路
公开(公告)号：US07279939B2
公开(公告)日：2007-10-09
申请号：US11113614
申请日：2005-04-25
申请人： Wayne Burleson , Vishak Venkotroman , Atul Maheshwari
发明人： Wayne Burleson , Vishak Venkotroman , Atul Maheshwari
IPC分类号： G01R19/00
CPC分类号： H03F3/45 , G11C7/062 , H03K3/356121 , H03K3/356165
摘要： Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG. 2, interconnect resistance 206 and the resistance of transistors 102 and 104 from FIG. 1, represented by the resistance of equivalent NMOS transistor 208 of FIG. 2.
摘要翻译：返回到图如图2所示，感测电路201表示必须感测互连上的信令的电路。 NMOS器件202总是导通，使得每当PMOS驱动器204导通时，存在连续的接地路径。由于泄漏功率比静态和动态功率小一个数量级，因此为了清楚起见，可以省略泄漏功率，尽管应该注意到，随着线路长度增加，互连电容增加，动态功率相对于线路长度增加。静态功率是由于图2所示的两个电阻之间的静电流的流动引起的。 2，互连电阻206和来自图2的晶体管102和104的电阻。由图1的等效NMOS晶体管208的电阻表示。 2。

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