专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20210012129A1 Method of registering and identifying a user of a voice-controlled device 有权
公开(公告)号：US20210012129A1
公开(公告)日：2021-01-14
申请号：US16508320
申请日：2019-07-11
申请人： Himanshu Kaul
发明人： Himanshu Kaul
IPC分类号： G06K9/00 , G10L17/22
摘要： The present invention is related to a method of registering and identifying a user of a voice-controlled device. The method comprising: registering the user of the device, determining at least one of a facial, eye and body features of the user upon determining at least one characteristic of a voice input from the user is below a threshold level, determining an output upon comparing the determined at least one of the facial, eye and body features of the user with a prestored information associated with the user in a database and identifying the user in accordance with the determined output.

2. 发明申请

US20150086007A1 COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
标题翻译：紧凑型低功耗高级加密标准电路
公开(公告)号：US20150086007A1
公开(公告)日：2015-03-26
申请号：US14035508
申请日：2013-09-24
申请人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
发明人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
IPC分类号： H04L9/30
CPC分类号： H04L9/0631 , H04L2209/24
摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
摘要翻译：公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。在一个实施例中，装置包括具有替换盒和累加器的加密单元。替代方案是对每个时钟周期的一个字节执行替换操作。累加器将累积四个字节，并在四个时钟周期内执行混合列操作。加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

3. 发明申请

US20140105303A1 Motion Estimation for Video Processing 审中-公开
标题翻译：视频处理的运动估计
公开(公告)号：US20140105303A1
公开(公告)日：2014-04-17
申请号：US13649560
申请日：2012-10-11
申请人： Himanshu Kaul , Mark A. Anders , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Mark A. Anders , Ram K. Krishnamurthy
IPC分类号： H04N7/32
CPC分类号： H04N19/43 , H04N19/567
摘要： In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.
摘要翻译：根据一些实施例，可以减少使用Haar，SAD和Hadamard变换的运动估计算法的复杂度。在一些实施例中，与现有技术相比可以减少求和的数量，并且可以用比较操作来替换一些现有的求和。在一些实施例中，为了平衡延迟和面积或能量或功率考虑，用比较代替添加。

4. 发明授权

US08284766B2 Multi-core processor and method of communicating across a die 有权
标题翻译：多核处理器和跨模块通信的方法
公开(公告)号：US08284766B2
公开(公告)日：2012-10-09
申请号：US11966327
申请日：2007-12-28
申请人： Mark Anders , Himanshu Kaul , Ram Krishnamurthy , Shekhar Borkar
发明人： Mark Anders , Himanshu Kaul , Ram Krishnamurthy , Shekhar Borkar
IPC分类号： H04L12/66
CPC分类号： G06F15/17375 , G06F15/7825 , Y02D10/12 , Y02D10/13
摘要： A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network.
摘要翻译：提供了一种多核管芯，其允许使用分组交换网络和电路交换网络的资源在管芯上传送分组。

5. 发明申请

US20080104164A1 Reconfigurable SIMD vector processing system 有权
标题翻译：可重构SIMD矢量处理系统
公开(公告)号：US20080104164A1
公开(公告)日：2008-05-01
申请号：US11586810
申请日：2006-10-26
申请人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
发明人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F2207/3828
摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.
摘要翻译：系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

6. 发明申请

US20050030066A1 TRANSITION-AWARE SIGNALING 失效
标题翻译：过渡信号
公开(公告)号：US20050030066A1
公开(公告)日：2005-02-10
申请号：US10389320
申请日：2003-03-14
申请人： Dennis Sylvester , Himanshu Kaul
发明人： Dennis Sylvester , Himanshu Kaul
IPC分类号： H03K3/3565 , H03K5/08 , H03K5/1534 , H03K5/22 , H04L25/02
CPC分类号： H04L25/0292 , H03K3/3565 , H03K5/084 , H03K5/088 , H03K5/1534
摘要： An improved receiver circuit for use on an integrated chip is disclosed. The receiver circuit is interposed in an interconnect line between electrical components in an integrated circuit. The receiver circuit has a transition detection circuit that generates a transition signal in response to a detection of a transition from a first state to a second state on the interconnect line and further generates the transition signal in response to a detection of a transition from the second state to the first state on said interconnect line. The receiver further includes an output signal control circuit that, in response to the transition signal, selectively outputs either a present state of said interconnect line or a next state of the interconnect line stored in the receiver.
摘要翻译：公开了一种用于集成芯片上的改进的接收机电路。接收器电路插入在集成电路中的电气部件之间的互连线中。接收器电路具有转换检测电路，其响应于在互连线上从第一状态到第二状态的转变的检测而产生转换信号，并且响应于检测到来自第二状态的转变而产生转换信号状态到所述互连线上的第一状态。接收机还包括输出信号控制电路，响应于转换信号，选择性地输出所述互连线的当前状态或存储在接收机中的互连线的下一状态。

7. 发明授权

US09634866B2 Architecture and method for hybrid circuit-switched and packet-switched router 有权
公开(公告)号：US09634866B2
公开(公告)日：2017-04-25
申请号：US14129544
申请日：2013-09-06
申请人： Mark A Anders , Gregory K Chen , Himanshu Kaul , Ram K Krishnamurthy , Shekhar Y Bokar
发明人： Mark A Anders , Gregory K Chen , Himanshu Kaul , Ram K Krishnamurthy , Shekhar Y Bokar
IPC分类号： H04L12/64 , H04L12/933
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.

8. 发明授权

US07519646B2 Reconfigurable SIMD vector processing system 有权
标题翻译：可重构SIMD矢量处理系统
公开(公告)号：US07519646B2
公开(公告)日：2009-04-14
申请号：US11586810
申请日：2006-10-26
申请人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
发明人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F2207/3828
摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.
摘要翻译：系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

9. 发明申请

US20090003428A1 Method and apparatus for treating a signal 有权
标题翻译：用于治疗信号的方法和装置
公开(公告)号：US20090003428A1
公开(公告)日：2009-01-01
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： H03K7/08
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译：一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。时钟相位的第一个数量与第二个时钟相位数不同。所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。

10. 发明申请

US20080181295A1 Method and apparatus for video processing 有权
标题翻译：视频处理方法和装置
公开(公告)号：US20080181295A1
公开(公告)日：2008-07-31
申请号：US11699241
申请日：2007-01-29
申请人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
发明人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
IPC分类号： H04B1/66
CPC分类号： H04N19/436 , H04N19/43
摘要： In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括使用冗余二进制数学压缩视频数据的方法。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式