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1. 发明申请

US20110062590A1 Chip Stacking Device Having Re-Distribution Layer 审中-公开
标题翻译：具有再分配层的芯片堆叠装置
公开(公告)号：US20110062590A1
公开(公告)日：2011-03-17
申请号：US12832776
申请日：2010-07-08
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： H01L23/482
CPC分类号： H01L23/525 , H01L23/3171 , H01L23/4828 , H01L23/5328 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product.
摘要翻译：芯片堆叠装置使用纳米颗粒银浆进行再分配互连，以通过沟槽填充或印刷形成具有低电阻的结构。因此，由于其低电阻，可以有效地降低电流流动后由于电压降引起的电不稳定性。而且，节省能源也减少了功耗。凭借其稳定的电气信号，其利用范围可以进一步扩大到高频产品。

2. 发明授权

US07838424B2 Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching 有权
标题翻译：使用干蚀刻提高晶圆级芯片级封装（WLCSP）芯片分离的可靠性
公开(公告)号：US07838424B2
公开(公告)日：2010-11-23
申请号：US11773277
申请日：2007-07-03
申请人： Tjandra Winata Karta , Steven Hsu , Chien-Hsiun Lee , Gene Wu , Jimmy Liang
发明人： Tjandra Winata Karta , Steven Hsu , Chien-Hsiun Lee , Gene Wu , Jimmy Liang
IPC分类号： H01L21/302
CPC分类号： H01L23/3178 , H01L21/561 , H01L23/3114 , H01L23/3185 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/13023 , H01L2224/16 , H01L2224/94 , H01L2924/01078 , H01L2924/01079 , H01L2924/10157 , H01L2924/14 , H01L2224/03 , H01L2224/11
摘要： An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.
摘要翻译：描述了改进的晶片级芯片级封装（WLCSP）工艺，其包括在半导体晶片的第一表面上形成多个导电柱。将一个或多个凹槽干蚀刻到半导体晶片的第一表面中，其中凹槽限定半导体晶片内的多个裸片中的每一个之间的至少一个边界。一层封装材料沉积在第一表面上。然后通过封装材料在每个凹槽中切割凹部，其中切割在半导体晶片的第二表面上留下一片半导体材料。然后将第二表面研磨以去除该半导体材料片，其中该材料的去除分离多个管芯。

3. 发明授权

US07642129B2 Ball-mounting method for coplanarity improvement in large package 失效
标题翻译：大包装球面安装方法的共面性改善
公开(公告)号：US07642129B2
公开(公告)日：2010-01-05
申请号：US11648926
申请日：2007-01-03
申请人： Jimmy Liang , Gene Wu , Steven Hsu
发明人： Jimmy Liang , Gene Wu , Steven Hsu
IPC分类号： H01L21/00
CPC分类号： H05K3/3457 , H01L21/4853 , H01L2224/16 , H01L2924/14 , H01L2924/15311 , H01L2924/3511 , H05K2203/0278 , H05K2203/043
摘要： A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.
摘要翻译：提供一种形成包装结构的方法及其形成的包装。该方法包括提供具有顶表面的封装并将焊球放置在封装的顶表面上。然后将共面表面放置在焊球上，其中该表面是非粘合的。对焊球进行回流处理，使得焊球的顶表面基本上共面。然后去除共面。

4. 发明申请

US20080103132A1 FUSED HETEROCYCLIC COMPOUNDS 有权
标题翻译：熔融杂环化合物
公开(公告)号：US20080103132A1
公开(公告)日：2008-05-01
申请号：US11924277
申请日：2007-10-25
申请人： Nicholas Carruthers , Wenying Chai , Xiaohu Deng , Curt Dvorak , Annette Kwok , Jimmy Liang , Neelakandha Mani , Dale Rudolph , Victoria Wong
发明人： Nicholas Carruthers , Wenying Chai , Xiaohu Deng , Curt Dvorak , Annette Kwok , Jimmy Liang , Neelakandha Mani , Dale Rudolph , Victoria Wong
IPC分类号： A61K31/55 , A61K31/437 , A61P25/00
CPC分类号： C07D487/04
摘要： Certain fused pyrrole- and pyrazole-containing heterocyclic compounds are serotonin modulators useful in the treatment of serotonin-mediated diseases.
摘要翻译：某些稠合的含吡咯和吡唑的杂环化合物是可用于治疗5-羟色胺介导的疾病的血清素调节剂。

5. 发明申请

US20050026903A1 CCK-1 receptor modulators 审中-公开
公开(公告)号：US20050026903A1
公开(公告)日：2005-02-03
申请号：US10881628
申请日：2004-06-30
申请人： Anusuya Choudhury , Jeffrey Grimm , Jimmy Liang , Neelakandha Mani , Kirk Sorgi
发明人： Anusuya Choudhury , Jeffrey Grimm , Jimmy Liang , Neelakandha Mani , Kirk Sorgi
IPC分类号： A61K31/16 , A61K31/19 , A61K31/445 , A61K31/55 , C07D231/12 , C07D401/04 , C07D401/06 , C07D403/04 , C07D403/06 , C07D403/12 , C07D405/04 , C07D405/06 , C07D405/10 , C07D405/14 , C07D409/06
CPC分类号： C07D231/12 , C07D401/04 , C07D401/06 , C07D403/06 , C07D403/12 , C07D405/04 , C07D405/06 , C07D405/10 , C07D405/14 , C07D409/06
摘要： There are provided by the present invention certain pyrazole based CCK-1 receptor modulators which have the general formula: wherein Ar is an aromatic or heteroaromatic group, X is a hydrocarbon linker, Y is a bond or hydrocarbon linker and R1, R2, R3, R4 and R5 are certain organic substituents, and methods of making the same.

6. 发明授权

US08184464B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US08184464B2
公开(公告)日：2012-05-22
申请号：US12780109
申请日：2010-05-14
申请人： Kuei-Wu Chu , Jimmy Liang , Leo Lu
发明人： Kuei-Wu Chu , Jimmy Liang , Leo Lu
IPC分类号： G11C5/06
CPC分类号： H01L23/48 , H01L24/06 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2924/01033 , H01L2924/01082 , H01L2924/014
摘要： A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired.
摘要翻译：闪存包括控制器单元和管芯。模具连接到控制器单元。每个模具包括上表面和下表面。每个管芯包括至少一个电源焊盘，至少一个接地焊盘，至少一个输入/输出焊盘，选择焊盘和在上表面和下表面中的每一个上的备用/忙碌焊盘。电源板连接到控制器单元。接地垫并联连接到电源板。输入/输出焊盘并联连接到接地焊盘。选择焊盘连接到控制器单元并且用如果需要切割的导线彼此连接。备用/繁忙焊盘连接到控制器单元，并使用可以切割的电线相互连接，如果需要的话。

7. 发明申请

US20110108983A1 Integrated Circuit 审中-公开
标题翻译：集成电路
公开(公告)号：US20110108983A1
公开(公告)日：2011-05-12
申请号：US12832765
申请日：2010-07-08
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： H01L23/498
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/0401 , H01L2224/05005 , H01L2224/0501 , H01L2224/0502 , H01L2224/05099 , H01L2224/0556 , H01L2224/05599 , H01L2224/11334 , H01L2924/0002 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit includes a die including contacts formed thereon. A first dielectric layer is formed on the die. The first dielectric layer includes apertures defined therein corresponding to the contacts. A second dielectric layer is formed on the second dielectric layer. The second dielectric layer includes apertures defined therein corresponding to the apertures of the first dielectric layer. Redistribution layers are located in the apertures of the first and second dielectric layers and connected to the contacts. A passivation layer is located on the second dielectric layer and the redistribution layers. The passivation layer includes apertures corresponding to the redistribution layers. A solder ball is located in each of the apertures of the passivation layer and connected to a related one of the redistribution layers.
摘要翻译：集成电路包括其上形成有触点的模具。在模具上形成第一电介质层。第一电介质层包括对应于触点的限定在其中的孔。第二电介质层形成在第二电介质层上。第二电介质层包括与第一介电层的孔对应的孔。再分布层位于第一和第二电介质层的孔中并连接到触点。钝化层位于第二介电层和再分配层上。钝化层包括对应于再分布层的孔。焊球位于钝化层的每个孔中并连接到相关的再分布层之一。

8. 发明申请

US20080197473A1 CHIP HOLDER WITH WAFER LEVEL REDISTRIBUTION LAYER 有权
标题翻译：带有水平重新分配层的芯片架
公开(公告)号：US20080197473A1
公开(公告)日：2008-08-21
申请号：US11675984
申请日：2007-02-16
申请人： Chen-Shien Chen , Chao-Hsiang Yang , Jimmy Liang , Han-Liang Tseng , Mirng-Ji Lii , Tjandra Winata Karta , Hua-Shu Wu
发明人： Chen-Shien Chen , Chao-Hsiang Yang , Jimmy Liang , Han-Liang Tseng , Mirng-Ji Lii , Tjandra Winata Karta , Hua-Shu Wu
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/5389 , H01L23/49816 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/92244 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/19107
摘要： A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.
摘要翻译：由硅，玻璃，其它陶瓷或其它合适材料形成的芯片保持架包括用于保持半导体芯片的多个凹槽。半导体芯片的接合焊盘形成在芯片保持器的围绕半导体芯片的区域上或上方，从而扩大接合面积。使用半导体晶片处理技术将接合焊盘连接到直接形成在半导体芯片上的内部接合焊盘。

9. 发明授权

US08424357B2 Easily stackable dies 有权
标题翻译：易于堆叠的模具
公开(公告)号：US08424357B2
公开(公告)日：2013-04-23
申请号：US12796101
申请日：2010-06-08
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： B21D37/16
CPC分类号： H01L25/0657 , H01L22/34 , H01L2225/06513 , H01L2225/06527 , H01L2225/06551 , H01L2924/0002 , H01L2924/00
摘要： A die includes upper contacts, lower contacts and conductive elements. The upper contacts are formed on an upper face of the die. The upper contacts include a non-connected upper contact and connected upper contacts. The lower contacts are formed on a lower face of the die. The lower contacts include a non-connected lower contact and connected lower contacts. Each of the conductive elements connects a related one of the connected upper contacts to a related one of the connected lower contacts.
摘要翻译：模具包括上触点，下触点和导电元件。上部触点形成在模具的上表面上。上部触点包括一个未连接的上触点和连接的上触点。下触点形成在模具的下表面上。下触点包括未连接的下触点和连接的下触点。每个导电元件将相关的一个连接的上触点连接到相连的下触点之一。

10. 发明申请

US20110062586A1 Chip for Reliable Stacking on another Chip 审中-公开
标题翻译：芯片可靠堆叠在另一个芯片上
公开(公告)号：US20110062586A1
公开(公告)日：2011-03-17
申请号：US12814458
申请日：2010-06-13
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： H01L23/538
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/16 , H01L2924/01079 , H01L2924/14 , H01L2924/00
摘要： A chip includes a device, a passivation layer, two dielectric layers, at least one upper redistribution layer, at least one lower redistribution layer, at least one tunnel, at least one conductor, a redistribution passivation layer and at least one solder ball. The device includes at least one pad. The tunnel is defined in the upper redistribution layer, the first dielectric layer, the passivation layer, the pad, the device, the chip, the second dielectric layer and the lower redistribution layer. The conductor is located in the tunnel and connected to the upper and lower redistribution layers. The redistribution passivation layer is located on the second dielectric layer, the lower redistribution layer and the conductor. The solder ball is located on a portion of the lower redistribution layer through an aperture defined in the redistribution passivation layer. The chip can be connected to a printed circuit board by the solder ball.
摘要翻译：芯片包括器件，钝化层，两个电介质层，至少一个上再分配层，至少一个下再分配层，至少一个隧道，至少一个导体，再分布钝化层和至少一个焊球。该装置包括至少一个垫。隧道定义在上再分配层，第一介电层，钝化层，焊盘，器件，芯片，第二介电层和下再分布层中。导体位于隧道内并与上，下重分布层连接。再分布钝化层位于第二介电层，下再分布层和导体上。焊球通过限定在再分布钝化层中的孔位于下再分布层的一部分上。芯片可以通过焊球连接到印刷电路板。

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