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1. 发明授权

US08440376B2 Exposure determining method, method of manufacturing semiconductor device, and computer program product 有权
标题翻译：曝光确定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US08440376B2
公开(公告)日：2013-05-14
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

2. 再颁专利

USRE43659E1 Method for making a design layout of a semiconductor integrated circuit 有权
标题翻译：制造半导体集成电路的设计布局的方法
公开(公告)号：USRE43659E1
公开(公告)日：2012-09-11
申请号：US12945672
申请日：2010-11-12
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则预定条件。

3. 发明授权

US08183119B2 Semiconductor device fabrication method using multiple mask patterns 有权
标题翻译：使用多个掩模图案的半导体器件制造方法
公开(公告)号：US08183119B2
公开(公告)日：2012-05-22
申请号：US12724118
申请日：2010-03-15
申请人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
发明人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
IPC分类号： H01L22/321
CPC分类号： G03F7/0035 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L21/823475 , H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
摘要翻译：在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。由此形成硬掩模图案（6）。由此，在非选择区域（6b）上形成具有露出掩模图案中的选择区域（6a）的开口（7a）的抗蚀剂图案（7）。通过进行选择蚀刻，只有通过开口（7a）露出的掩模图案（6a）变薄，通过使用掩模图案（6）蚀刻工作膜（3）。由此形成工作胶片图案（8），其包括具有限制曝光分辨率的尺寸宽度的宽图案部分（8a）和尺寸不超过限制的尺寸的纤薄图案部分（8a）曝光分辨率。

4. 再颁专利

USRE42294E1 Semiconductor integrated circuit designing method and system using a design rule modification 有权
标题翻译：半导体集成电路设计方法和系统采用设计规则修改
公开(公告)号：USRE42294E1
公开(公告)日：2011-04-12
申请号：US10819338
申请日：2004-04-07
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5081
摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则预定条件。

5. 发明申请

US20110065028A1 PATTERN GENERATING METHOD, MANUFACTURING METHOD OF MASK, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：图案生成方法，掩模制造方法和半导体器件的制造方法
公开(公告)号：US20110065028A1
公开(公告)日：2011-03-17
申请号：US12874756
申请日：2010-09-02
申请人： Katsuyoshi KODERA , Satoshi TANAKA , Toshiya KOTANI , Soichi INOUE
发明人： Katsuyoshi KODERA , Satoshi TANAKA , Toshiya KOTANI , Soichi INOUE
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F1/36
摘要： According to the embodiments, each of a main pattern of a mask to be transferred onto a substrate by using a lithography process, a first assist pattern that improves a resolution of an on-substrate pattern obtained by transferring the main pattern onto the substrate, and a second assist pattern that suppresses a transfer property of the first assist pattern onto the substrate is placed as a mask pattern.
摘要翻译：根据实施例，通过使用光刻工艺将要转印到基板上的掩模的主图案，提高通过将主图案转印到基板上而获得的基板上图案的分辨率的第一辅助图案，以及将第一辅助图案的转印特性抑制在基板上的第二辅助图案作为掩模图案。

6. 发明申请

US20100067777A1 EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD 审中-公开
标题翻译：评估模式生成方法，计算机程序产品和模式验证方法
公开(公告)号：US20100067777A1
公开(公告)日：2010-03-18
申请号：US12536900
申请日：2009-08-06
申请人： Katsuyoshi Kodera , Satoshi Tanaka , Shimon Maeda , Suigen Kyoh , Soichi Inoue , Ryuji Ogawa
发明人： Katsuyoshi Kodera , Satoshi Tanaka , Shimon Maeda , Suigen Kyoh , Soichi Inoue , Ryuji Ogawa
IPC分类号： G06K9/00
CPC分类号： G03F1/44 , G03F1/36
摘要： An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.
摘要翻译： 1.一种评价图案生成方法，包括将评价对象图案的周边区域划分为多个网格; 当将掩模函数值赋予预定网格时，通过光刻处理将评估对象图案转印到晶片上时，计算电路图案的图像强度; 计算网格的掩码函数值，使得影响评估对象图案对晶片的转印性能的光学图像特征量被设置为图像强度的图像强度的成本函数满足预定参考，当评估目标模式的光刻性能评估; 以及生成与所述掩模功能值对应的评估图案。

7. 发明授权

US07499582B2 Method for inspecting a defect in a photomask, method for manufacturing a semiconductor device and method for producing a photomask 失效
标题翻译：用于检查光掩模中的缺陷的方法，用于制造半导体器件的方法和用于制造光掩模的方法
公开(公告)号：US07499582B2
公开(公告)日：2009-03-03
申请号：US10878384
申请日：2004-06-29
申请人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
发明人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
IPC分类号： G06K9/00
CPC分类号： G03F1/84 , G06T7/001 , G06T2207/30148
摘要： There is disclosed a method for inspecting a defect in a photomask which is produced by using a graphic data, that matches mask data or is produced by subjecting mask data to correction of a process conversion difference relating to at least a line width. The method includes the following steps. Inspection data is produced by correcting a pattern of mask data so as to substantially match a planar shape of a pattern of a photomask to be produced by using the graphic data. A pattern of a produced photomask is compared with a pattern of the inspection data. Portions where planar shapes of the pattern of the inspection data and the pattern of the produced photomask do not match are extracted. A defect is distinguished from the portions where the planer shapes do not match.
摘要翻译：公开了一种用于检查光掩模中的缺陷的方法，其通过使用匹配掩模数据的图形数据或通过对掩模数据进行校正至少与线宽相关的处理转换差来产生。该方法包括以下步骤。通过校正掩模数据的图案以便通过使用图形数据基本上匹配要产生的光掩模的图案的平面形状来产生检查数据。将生成的光掩模的图案与检查数据的图案进行比较。提取检查数据的图案的平面形状和所生成的光掩模的图案不匹配的部分。缺陷与刨床形状不匹配的部分不同。

8. 发明申请

US20090021711A1 METHOD OF INSPECTING EXPOSURE SYSTEM AND EXPOSURE SYSTEM 审中-公开
标题翻译：检查曝光系统和曝光系统的方法
公开(公告)号：US20090021711A1
公开(公告)日：2009-01-22
申请号：US12173943
申请日：2008-07-16
申请人： Takashi Sato , Soichi Inoue
发明人： Takashi Sato , Soichi Inoue
IPC分类号： G03B27/42 , G01B11/14
CPC分类号： G03F7/706 , G03B27/42 , G03F1/44
摘要： A method of inspecting an exposure system uses a mask pattern including a first and a second mask pattern, the first pattern being formed in a line-and-space of a first pitch, the second pattern being disposed in parallel with the first mask pattern and formed in a line-and-space of a second pitch. The method includes illuminating the mask pattern with inspection light at a first angle with the optical axis of the illumination light from a light source, allowing the first mask pattern to diffract the inspection light to generate first diffraction light, and allowing the second mask pattern to diffract the inspection light to generate second diffraction light. The first angle is to allow the first diffraction light to be diffracted asymmetrically with the optical axis into the projection optical system and the second diffraction light to be diffracted symmetrically with the optical axis into the projection optical system.
摘要翻译：检查曝光系统的方法使用包括第一和第二掩模图案的掩模图案，第一图案形成在第一间距的直线和间隔中，第二图案与第一掩模图案平行设置，形成在第二间距的线和空间中。该方法包括用来自光源的照明光的光轴以第一角度的检查光照亮掩模图案，允许第一掩模图案衍射检查光以产生第一衍射光，并允许第二掩模图案衍射检查光以产生第二衍射光。第一角度是允许第一衍射光被光轴不对称地衍射到投影光学系统中，并且第二衍射光将被光轴对称地衍射到投影光学系统中。

9. 发明申请

US20080232671A1 MASK PATTERN VERIFYING METHOD 有权
标题翻译：掩模图验证方法
公开(公告)号：US20080232671A1
公开(公告)日：2008-09-25
申请号：US12052066
申请日：2008-03-20
申请人： Mitsuyo ASANO , Shinji Yamaguchi , Satoshi Tanaka , Soichi Inoue , Masamitsu Itoh , Osamu Ikenaga
发明人： Mitsuyo ASANO , Shinji Yamaguchi , Satoshi Tanaka , Soichi Inoue , Masamitsu Itoh , Osamu Ikenaga
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G03F1/86 , G06T2207/10056 , G06T2207/30148
摘要： A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information.
摘要翻译：掩模图案验证方法包括从掩模图案的设计数据获得关于热点的第一信息，获得关于实际形成在光掩模上的掩模图案的第二信息，以及确定实际形成在光掩模上的掩模图案的测量点基于第一和第二信息。

10. 发明授权

US07371483B2 Method for manufacturing mask for focus monitoring, and method for manufacturing semiconductor device 失效
标题翻译：用于制造焦点监视用掩模的方法以及半导体装置的制造方法
公开(公告)号：US07371483B2
公开(公告)日：2008-05-13
申请号：US10830399
申请日：2004-04-23
申请人： Shingo Kanamitsu , Takashi Hirano , Kyoko Izuha , Soichi Inoue , Shinichi Ito
发明人： Shingo Kanamitsu , Takashi Hirano , Kyoko Izuha , Soichi Inoue , Shinichi Ito
IPC分类号： G03F9/00
CPC分类号： G03F1/32 , G03F1/44 , Y10S430/143
摘要： Disclosed is a method for manufacturing a mask for focus monitoring, comprising forming a first opening portion and a second opening portion in a surface region of a transparent substrate, the second opening portion having a pattern shape corresponding to a pattern shape of the first opening portion, and being surrounded by a stack film formed of a halftone film on the transparent substrate and an opaque film on the halftone film, and radiating a charged beam onto a first region which includes an edge of the second opening portion and inside and outside regions which are respectively located inward and outward of the edge of the second opening portion, to etch that part of the transparent substrate which corresponds to the inside region.
摘要翻译：本发明公开了一种制造用于聚焦监测的掩模的方法，包括在透明基板的表面区域中形成第一开口部分和第二开口部分，所述第二开口部分具有与第一开口部分的图案形状对应的图案形状并且被由透明基板上的半色调膜形成的叠层膜和半色调膜上的不透明膜包围，并且将带电束辐射到包括第二开口部分的边缘和内部和外部区域的第一区域上，分别位于第二开口部分的边缘的内侧和外侧，以蚀刻对应于内部区域的透明基板的那部分。

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