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1. 发明申请

US20110029937A1 PATTERN EVALUATING METHOD, PATTERN GENERATING METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：模式评估方法，图案生成方法和计算机程序产品
公开(公告)号：US20110029937A1
公开(公告)日：2011-02-03
申请号：US12836235
申请日：2010-07-14
申请人： Katsuyoshi KODERA , Satoshi TANAKA , Toshiya KOTANI , Shigeki NOJIMA , Soichi INOUE
发明人： Katsuyoshi KODERA , Satoshi TANAKA , Toshiya KOTANI , Shigeki NOJIMA , Soichi INOUE
IPC分类号： G06F17/50
CPC分类号： G03F7/70441
摘要： A pattern evaluating method includes generating a proximity pattern that affects a resolution performance of a circuit pattern around a lithography target pattern of the circuit pattern to be formed on the substrate, generating distribution information on a distribution of an influence degree to the resolution performance of the circuit pattern by using the lithography target pattern, calculating the influence degree to the resolution performance of the circuit pattern by the proximity pattern as a score by comparing the distribution information with the proximity pattern, and evaluating whether the proximity pattern is placed at an appropriate position in accordance with the circuit pattern based on the score.
摘要翻译：模式评估方法包括：生成接近图案，其影响围绕要形成在基板上的电路图案的光刻目标图案周围的电路图案的分辨率性能，产生关于影响程度分布的分布信息，通过使用光刻目标图案，通过将分布信息与接近图案进行比较，计算通过邻近图案作为分数的电路图案的分辨率性能的影响程度，以及评估接近图案是否位于适当位置根据电路图案的分数。

2. 发明申请

US20110065028A1 PATTERN GENERATING METHOD, MANUFACTURING METHOD OF MASK, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：图案生成方法，掩模制造方法和半导体器件的制造方法
公开(公告)号：US20110065028A1
公开(公告)日：2011-03-17
申请号：US12874756
申请日：2010-09-02
申请人： Katsuyoshi KODERA , Satoshi TANAKA , Toshiya KOTANI , Soichi INOUE
发明人： Katsuyoshi KODERA , Satoshi TANAKA , Toshiya KOTANI , Soichi INOUE
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F1/36
摘要： According to the embodiments, each of a main pattern of a mask to be transferred onto a substrate by using a lithography process, a first assist pattern that improves a resolution of an on-substrate pattern obtained by transferring the main pattern onto the substrate, and a second assist pattern that suppresses a transfer property of the first assist pattern onto the substrate is placed as a mask pattern.
摘要翻译：根据实施例，通过使用光刻工艺将要转印到基板上的掩模的主图案，提高通过将主图案转印到基板上而获得的基板上图案的分辨率的第一辅助图案，以及将第一辅助图案的转印特性抑制在基板上的第二辅助图案作为掩模图案。

3. 发明申请

US20120244717A1 RESIN REMOVAL METHOD, RESIN REMOVAL APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：树脂去除方法，树脂去除装置和制造半导体器件的方法
公开(公告)号：US20120244717A1
公开(公告)日：2012-09-27
申请号：US13233583
申请日：2011-09-15
申请人： Yingkang ZHANG , Katsuyoshi KODERA , Tetsuaki MATSUNAWA , Masanori TAKAHASHI
发明人： Yingkang ZHANG , Katsuyoshi KODERA , Tetsuaki MATSUNAWA , Masanori TAKAHASHI
IPC分类号： H01L21/268 , B29C35/08
CPC分类号： G03F7/427 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： According to one embodiment, a resin removal method is provided. In the resin removal method, near-field light is generated in a local area of a pattern concave-convex portion on a pattern master used for imprinting by irradiating the pattern master with ultraviolet light in an ashing gas atmosphere which removes resin attached to the pattern master. Then, the resin is removed from the pattern master by using the ashing gas and the near-field light.
摘要翻译：根据一个实施例，提供树脂去除方法。在树脂去除方法中，通过在附着于图案的灰色气体气氛中用紫外线照射图案母版的图案母版上的图案凹凸部分的局部区域中产生近场光，主。然后，通过使用灰化气体和近场光从图案母版去除树脂。

4. 发明申请

US20110209107A1 MASK-LAYOUT CREATING METHOD, APPARATUS THEREFOR, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：掩模制作方法，其设备和计算机程序产品
公开(公告)号：US20110209107A1
公开(公告)日：2011-08-25
申请号：US13028525
申请日：2011-02-16
申请人： Katsuyoshi KODERA , Chikaaki Kodama
发明人： Katsuyoshi KODERA , Chikaaki Kodama
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.
摘要翻译：根据一个实施例，设置在光刻过程中很可能是危险点的设计布局，相对于集合设计布局设置用于生成掩模布局的相干映射内核，基于该集合创建相干映射相干映射内核和集合设计布局，从创建的相干图中提取辅助模式并对其进行整形以生成掩模布局，定义用于评估掩模布局优化度的成本函数COST，使用成本函数以及从相干图提取和整形辅助图案中的相干图核心和参数中的至少一个被改变，直到使用成本函数评估的掩模布局被优化为止。

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