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1. 发明申请

US20050025351A1 Method for inspecting a defect in a photomask, method for manufacturing a semiconductor device and method for producing a photomask 失效
标题翻译：用于检查光掩模中的缺陷的方法，用于制造半导体器件的方法和用于制造光掩模的方法
公开(公告)号：US20050025351A1
公开(公告)日：2005-02-03
申请号：US10878384
申请日：2004-06-29
申请人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
发明人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
IPC分类号： G03F1/20 , G03F1/84 , G03F1/86 , G06K9/00 , G06T7/00 , H01L21/027
CPC分类号： G03F1/84 , G06T7/001 , G06T2207/30148
摘要： There is disclosed a method for inspecting a defect in a photomask which is produced by using a graphic data, that matches mask data or is produced by subjecting mask data to correction of a process conversion difference relating to at least a line width. The method includes the following steps. Inspection data is produced by correcting a pattern of mask data so as to substantially match a planar shape of a pattern of a photomask to be produced by using the graphic data. A pattern of a produced photomask is compared with a pattern of the inspection data. Portions where planar shapes of the pattern of the inspection data and the pattern of the produced photomask do not match are extracted. A defect is distinguished from the portions where the planer shapes do not match.
摘要翻译：公开了一种用于检查光掩模中的缺陷的方法，其通过使用匹配掩模数据的图形数据或通过对掩模数据进行校正至少与线宽相关的处理转换差来产生。该方法包括以下步骤。通过校正掩模数据的图案以便通过使用图形数据基本上匹配要产生的光掩模的图案的平面形状来产生检查数据。将生成的光掩模的图案与检查数据的图案进行比较。提取检查数据的图案的平面形状和所生成的光掩模的图案不匹配的部分。缺陷与刨床形状不匹配的部分不同。

2. 发明授权

US07499582B2 Method for inspecting a defect in a photomask, method for manufacturing a semiconductor device and method for producing a photomask 失效
标题翻译：用于检查光掩模中的缺陷的方法，用于制造半导体器件的方法和用于制造光掩模的方法
公开(公告)号：US07499582B2
公开(公告)日：2009-03-03
申请号：US10878384
申请日：2004-06-29
申请人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
发明人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
IPC分类号： G06K9/00
CPC分类号： G03F1/84 , G06T7/001 , G06T2207/30148
摘要： There is disclosed a method for inspecting a defect in a photomask which is produced by using a graphic data, that matches mask data or is produced by subjecting mask data to correction of a process conversion difference relating to at least a line width. The method includes the following steps. Inspection data is produced by correcting a pattern of mask data so as to substantially match a planar shape of a pattern of a photomask to be produced by using the graphic data. A pattern of a produced photomask is compared with a pattern of the inspection data. Portions where planar shapes of the pattern of the inspection data and the pattern of the produced photomask do not match are extracted. A defect is distinguished from the portions where the planer shapes do not match.
摘要翻译：公开了一种用于检查光掩模中的缺陷的方法，其通过使用匹配掩模数据的图形数据或通过对掩模数据进行校正至少与线宽相关的处理转换差来产生。该方法包括以下步骤。通过校正掩模数据的图案以便通过使用图形数据基本上匹配要产生的光掩模的图案的平面形状来产生检查数据。将生成的光掩模的图案与检查数据的图案进行比较。提取检查数据的图案的平面形状和所生成的光掩模的图案不匹配的部分。缺陷与刨床形状不匹配的部分不同。

3. 发明申请

US20090199148A1 Pattern-producing method for semiconductor device 有权
公开(公告)号：US20090199148A1
公开(公告)日：2009-08-06
申请号：US12385454
申请日：2009-04-08
申请人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
发明人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.

4. 发明授权

US07523437B2 Pattern-producing method for semiconductor device 失效
标题翻译：半导体器件的图案制作方法
公开(公告)号：US07523437B2
公开(公告)日：2009-04-21
申请号：US11012492
申请日：2004-12-16
申请人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
发明人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
IPC分类号： G06F16/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.
摘要翻译：公开了一种制造用于半导体器件的图案的方法，包括提取图案布局的一部分，扰乱包含在图案布局部分中的图案以产生扰动图案，校正扰动图案，预测第一图案，为形成在晶片上，从校正的扰动图案获取扰动图案和第一图案之间的第一个差异，以及存储关于包含关于第一个差异的信息的扰动图案的信息。

5. 发明授权

US07194704B2 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US07194704B2
公开(公告)日：2007-03-20
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

6. 发明授权

US07966584B2 Pattern-producing method for semiconductor device 有权
标题翻译：半导体器件的图案制作方法
公开(公告)号：US07966584B2
公开(公告)日：2011-06-21
申请号：US12385454
申请日：2009-04-08
申请人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
发明人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.
摘要翻译：公开了一种制造用于半导体器件的图案的方法，包括提取图案布局的一部分，扰乱包含在图案布局部分中的图案以产生扰动图案，校正扰动图案，预测第一图案，为形成在晶片上，从校正的扰动图案获取扰动图案和第一图案之间的第一个差异，以及存储关于包含关于第一个差异的信息的扰动图案的信息。

7. 发明申请

US20050204322A1 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US20050204322A1
公开(公告)日：2005-09-15
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

8. 发明申请

US20050134866A1 Pattern-producing method for semiconductor device 失效
标题翻译：半导体器件的图案制作方法
公开(公告)号：US20050134866A1
公开(公告)日：2005-06-23
申请号：US11012492
申请日：2004-12-16
申请人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
发明人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , G01B11/14
CPC分类号： G03F1/36 , G03F7/70441
摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.
摘要翻译：公开了一种制造用于半导体器件的图案的方法，包括提取图案布局的一部分，扰乱包含在图案布局部分中的图案以产生扰动图案，校正扰动图案，预测第一图案，为形成在晶片上，从校正的扰动图案获取扰动图案和第一图案之间的第一个差异，以及存储关于包含关于第一个差异的信息的扰动图案的信息。

9. 发明授权

US07029799B2 Exposure method for forming pattern for IC chips on reticle by use of master masks 有权
公开(公告)号：US07029799B2
公开(公告)日：2006-04-18
申请号：US10118050
申请日：2002-04-09
申请人： Suigen Kyoh , Soichi Inoue
发明人： Suigen Kyoh , Soichi Inoue
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F7/70466 , G03F1/00 , G03F1/50
摘要： There is provided a method which forms master masks used when a pattern of size larger than a region which can be exposed at one time is exposed on a to-be-exposed object. The pattern of the size larger than the region which can be exposed at one time is divided into a region of low repetitiveness and a region of high repetitiveness. A pattern of the region of low repetitiveness is drawn on at least one first master mask. Further, a pattern of the region of high repetitiveness is drawn on at least one second master mask.

10. 发明授权

US06542237B1 Exposure method for making precision patterns on a substrate 失效
标题翻译：在基板上制作精密图案的曝光方法
公开(公告)号：US06542237B1
公开(公告)日：2003-04-01
申请号：US09520630
申请日：2000-03-07
申请人： Suigen Kyoh , Iwao Higashikawa , Soichi Inoue
发明人： Suigen Kyoh , Iwao Higashikawa , Soichi Inoue
IPC分类号： G01B1100
CPC分类号： G03F9/7003
摘要： An exposure method forms a plurality of patterns on a substrate, which is set on a stage of an exposure apparatus, through at least one mask. The method equalizes first positional linear error components of a pattern to be formed by the mask on a first coordinate system defined on the substrate to second positional linear error components of the pattern on a second coordinate system on which the stage is moved, by correcting coordinates for moving the stage on the second coordinate system. The method is capable of aligning the boundaries of patterns with each other on the substrate, to leave only positional linear error components on the patterns. These positional linear error components are removable to leave minimum random residual errors on the patterns, and therefore, the patterns on the substrate are precisely at specified positions.
摘要翻译：曝光方法通过至少一个掩模在设置在曝光装置的台上的基板上形成多个图案。该方法通过在基板上定义的第一坐标系上的掩模形成的图案的第一位置线性误差分量与移动台上的第二坐标系上的图案的第二位置线性误差分量相等，用于在第二坐标系上移动舞台。该方法能够使衬底上的图案的边界彼此对准，从而在图案上仅留下位置线性误差分量。这些位置线性误差分量是可去除的，以在图案上留下最小的随机残留误差，因此衬底上的图案精确地在指定位置。

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