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1. 发明授权

US07137085B1 Wafer level global bitmap characterization in integrated circuit technology development 有权
标题翻译：晶圆级全局位图表征在集成电路技术开发中
公开(公告)号：US07137085B1
公开(公告)日：2006-11-14
申请号：US10858739
申请日：2004-06-01
申请人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
发明人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31718 , G01R31/318511
摘要： A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.
摘要翻译：用于晶片级全局位图表征的系统和方法包括从半导体晶片确定芯片级缺陷数据位图，以及将芯片级缺陷数据位图合并到表征基本上整个晶片故障配置的全局晶片级位图中。然后分析全球晶圆级位图并与其他全球晶圆级位图进行比较，以开发相关性，并开发全球晶圆级位图定义，用于进行晶圆到晶片，船对船和批次位图中的至少一个，基于全球晶圆级位图定义的批量处理分析。

2. 发明授权

US08725748B1 Method and system for storing and retrieving semiconductor tester information 有权
标题翻译：存储和检索半导体测试仪信息的方法和系统
公开(公告)号：US08725748B1
公开(公告)日：2014-05-13
申请号：US10929038
申请日：2004-08-27
申请人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
发明人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
IPC分类号： G06F17/30
CPC分类号： G01R31/318314
摘要： A tester information tester information processing system provides test equipment for generating test data. A markup language encoder connected to the test equipment encodes the test data for storage in an object-oriented database management system connected to the markup language encoder, and a user interface is operatively connected to the object-oriented database management system for retrieval of the test data.
摘要翻译：测试仪信息测试仪信息处理系统提供测试设备生成测试数据。连接到测试设备的标记语言编码器对连接到标记语言编码器的面向对象的数据库管理系统中存储的测试数据进行编码，并且用户界面可操作地连接到面向对象的数据库管理系统以检索测试数据。

3. 发明授权

US07634127B1 Efficient storage of fail data to aid in fault isolation 失效
标题翻译：故障数据的有效存储有助于故障隔离
公开(公告)号：US07634127B1
公开(公告)日：2009-12-15
申请号：US10884333
申请日：2004-07-01
申请人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
发明人： Srikanth Sundararajan , Siu May Ho , Shivananda S. Shetty
IPC分类号： G06K9/00 , G01R31/26
CPC分类号： G01R31/318511 , G01R31/2894 , G06T11/206
摘要： A method and system for fault isolation in semiconductor with devices thereon includes determining test data from a plurality of semiconductor devices and creating a failure bitmap of locations of the plurality of semiconductor devices and test data in a vector graphic CAD format. The vector graphic CAD format allows storage of test data on multiple layers.
摘要翻译：一种用于其中装置的半导体中的故障隔离的方法和系统，包括：确定来自多个半导体器件的测试数据，并以向量图形CAD格式创建多个半导体器件的位置以及测试数据的故障位图。矢量图形CAD格式允许在多层存储测试数据。

4. 发明授权

US6028994A Method for predicting performance of microelectronic device based on electrical parameter test data using computer model 失效
标题翻译：基于电参数测试数据使用计算机模型预测微电子器件性能的方法
公开(公告)号：US6028994A
公开(公告)日：2000-02-22
申请号：US73619
申请日：1998-05-06
申请人： Yeng-Kaung Peng , Chern-Jiann Lee , Siu-May Ho
发明人： Yeng-Kaung Peng , Chern-Jiann Lee , Siu-May Ho
IPC分类号： G01R31/30 , H01L21/66 , G06F9/455
CPC分类号： H01L22/20 , G01R31/30
摘要： Electrical parameter testing and performance testing are performed on a plurality of microelectronic devices to obtain parametric values and performance values respectively. The parametric values are applied as inputs to a computer program such as a back propagation neural network engine which generates a performance prediction model by self-learning that implements a function relating the performance values to the parametric values. The model is used to predict the performance of devices being fabricated by performing electrical parameter testing on these devices and applying the resulting parametric values to the model as inputs to produce predicted performance values as outputs. The model can be configured to produce predicted performance values as percentages of devices having speed or other parameters in predetermined respective ranges. The model can be further configured to produce predicted performance values as percentages of devices having different types of defects. The model can be improved by self-learning using additional test values. The model can also be used to identify parameters which result in low performance and improve devices being fabricated by adjusting the corresponding process parameters.
摘要翻译：在多个微电子器件上执行电参数测试和性能测试，以分别获得参数值和性能值。将参数值作为输入应用于计算机程序，例如反向传播神经网络引擎，其通过自学习产生性能预测模型，该模型实现与性能值相关的参数值。该模型用于通过对这些器件执行电气参数测试来预测正在制造的器件的性能，并将所得到的参数值作为输入应用到模型中，以产生预测的性能值作为输出。该模型可以被配置为产生预测的性能值，作为具有预定相应范围内的速度或其他参数的设备的百分比。该模型可进一步配置为产生具有不同类型缺陷的设备的百分比的预测性能值。该模型可以通过使用附加测试值的自学习来改进。该模型还可用于识别导致低性能的参数，并通过调整相应的过程参数来改进制造的器件。

5. 发明授权

US5787190A Method and apparatus for pattern recognition of wafer test bins 失效
标题翻译：晶圆测试箱的模式识别方法和装置
公开(公告)号：US5787190A
公开(公告)日：1998-07-28
申请号：US884316
申请日：1997-06-27
申请人： Yeng-Kaung Peng , Siu-May Ho , Ying Shiau
发明人： Yeng-Kaung Peng , Siu-May Ho , Ying Shiau
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.
摘要翻译：自动化系统和程序处理半导体晶片的晶圆测试箱数据，以制定统计学显着水平的故障模式。诸如神经引擎或神经网络的处理器收集晶片测试箱结果以产生N / N晶片图，以与从晶片电测试，晶片级可靠性测试和在线缺陷分析产生的晶片图相关联。由处理器产生的N / N晶片图与从另一半导体测试仪生成的晶片图进行交叉检查，以制定可能的重叠故障模式。通过执行故障分析，找出故障模式的根本原因进一步分析确认的故障模式。包含故障模式和故障模式的根本原因的报告被发送回制造厂，以调整制造工艺以提高未来批次的半导体晶片的总体产量。报告也存储在模式数据库中，用作库以供以前识别的故障模式的参考，从而绕过对故障模式匹配进行故障分析的需要。

6. 发明授权

US06774395B1 Apparatus and methods for characterizing floating body effects in SOI devices 失效
标题翻译：用于表征SOI器件中浮体效应的装置和方法
公开(公告)号：US06774395B1
公开(公告)日：2004-08-10
申请号：US10345007
申请日：2003-01-15
申请人： Hung-Jen Lin , W Eugene Hill , Mario M. Pelella , Chern-Jann Lee , Srikanth Sundararajan , Siu May Ho
发明人： Hung-Jen Lin , W Eugene Hill , Mario M. Pelella , Chern-Jann Lee , Srikanth Sundararajan , Siu May Ho
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.
摘要翻译：描述了用于表征SOI晶片中的浮体延迟效应的方法，包括向晶片中的浮体和绑定的主体链提供脉冲边缘，根据一个或多个浮体装置存储绑定的身体链数据，并表征浮动根据存储的绑定的身体链数据的身体延迟效应。还描述了测试装置，其包括浮体体链，其包括在晶片中制造的多个串联连接的浮体反相器或NAND门，以及包括多个串联连接的绑定体装置的晶片的绑定体链。存储装置与绑定的身体装置和一个或多个浮体装置相耦合，并根据来自浮体的一个或多个信号，操作以从捆绑的身体装置中存储绑定的身体链数据。

7. 发明授权

US5598341A Real-time in-line defect disposition and yield forecasting system 失效
标题翻译：实时在线缺陷处置和收益预测系统
公开(公告)号：US5598341A
公开(公告)日：1997-01-28
申请号：US401490
申请日：1995-03-10
申请人： Zhi-Min Ling , Thao Vo , Siu-May Ho , Ying Shiau , Yeng-Kaung Peng , Yung-Tao Lin
发明人： Zhi-Min Ling , Thao Vo , Siu-May Ho , Ying Shiau , Yeng-Kaung Peng , Yung-Tao Lin
IPC分类号： G01N21/95 , G03F7/20 , H01L21/00 , H01L21/66 , G06F19/00
CPC分类号： H01L21/67288 , G01N21/9501 , G03F7/705 , G03F7/7065 , H01L21/67276 , H01L22/20
摘要： A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information. The yield management station also determines a priority for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the layers.
摘要翻译：具有层包含装置的半导体晶片的实时在线缺陷布置和产量预测系统包括在线制造检查工具，设计审查站和产量管理站。在线制造检查工具检查半导体晶片的至少两层，并且产生包括其中为每个这些层引入的颗粒尺寸，颗粒位置和颗粒数量的第一信息。设计检查站检查半导体晶片的层，并产生包括每个层的布局的第二信息。产量管理站可操作地连接到在线制造检查工具和设计审查站。产量管理站从设计检查站检索来自在线制造检验工具的第一信息和第二信息。收益管理站使用第一和第二信息确定每个层中的设备的多个杀手缺陷中的至少一个或每个层的缺陷敏感区域索引。收益管理站还根据每个层的凶手缺陷数量和缺陷敏感区域索引中的至少一个来确定分析至少两个层中的每一个的优先级。

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